On Thu, Feb 08, 2018 at 06:10:31PM -0500, Hans-Peter Nilsson wrote: > On Wed, 7 Feb 2018, Segher Boessenkool wrote: > > Hi Mike, > > > > On Tue, Feb 06, 2018 at 04:34:08PM -0500, Michael Meissner wrote: > > > Here is the patch reworked. It bootstraps on both little/big endian > > > power8, > > > and all of the tests run. Can I install this into trunk now, and into > > > GCC 7 > > > after a soak period (along with the previous patch)? > > > > > +;; If have ISA 3.0, QI/HImode values can go in both VSX registers and GPR > > > > "If we have"? > > > > > + [(set (match_operand:QHSI 0 "memory_operand" "=Z") > > > + (any_fix:QHSI (match_operand:SFDF 1 "gpc_reg_operand" "wa"))) > > > + (clobber (match_scratch:SI 2 "=wa"))] > > > + "((<QHSI:MODE>mode == SImode && TARGET_P8_VECTOR) > > > + || (<QHSI:MODE>mode != SImode && TARGET_P9_VECTOR))" > > > > This is the same as > > > > "(<QHSI:MODE>mode == SImode && TARGET_P8_VECTOR) || TARGET_P9_VECTOR" > > Umm, sorry for chiming in here with zero rs6000 knowledge and I > might be missing something trivial but...what wouldn't that misfire for > "<QHSI:MODE>mode == SImode && ! TARGET_P8_VECTOR && TARGET_P9_VECTOR" ? > > (Is that invalid or not applicable or don't care or something?)
TARGET_P9_VECTOR requires TARGET_P8_VECTOR. Basically when we are converting SF/DFmode to SImode, we want to allow it on ISA 2.07 (-mcpu=power8). If we are converting to SF/DFmode to HI/QImode, we require ISA 3.0 (-mcpu=power9). The reason is that we don't have the instructions to do 32-bit integer store and 32-bit integer sign/zero extended load instructions to all of the vector and floating point registers until ISA 2.07. Because of that, we don't allow SImode in the vector and floating point registers until ISA 2.07. In processors before power8, we had to do a store 64-bit integer on the stack and then load up the 32-bit value into the GPR registers. However, ISA 2.07 does not have instructions to store or load 8/16-bit values that can be conveniently used. ISA 3.0 added 8/16-bit store, 8/16-bit zero extended load, and 8/16-bit sign extend instructions. So in ISA 3.0, we allow QI/HImode to go in vector registers. In ISA 2.06 (-mcpu=power7) we had to use UNSPECs to hide the convert floating point scalar to 32-bit signed/unsigned instruction instructions because we didn't allow the base type into the register. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
