On Tue, Feb 06, 2018 at 11:15:21AM -0600, Segher Boessenkool wrote:
> Hi!
>
> On Mon, Feb 05, 2018 at 05:57:51PM -0500, Michael Meissner wrote:
> > > We have
> > >
> > > (define_code_attr su [(sign_extend "s")
> > > (zero_extend "u")
> > > (fix "s")
> > > (unsigned_fix "s")
> > > (float "s")
> > > (unsigned_float "u")])
> > >
> > > and "s" for unsigned_fix seems like it should be "u". Very surprising
> > > otherwise (if this is needed in some case, it should just write "s" there
> > > instead of "<su>").
>
> What about this?
As we discussed before, this was a bug, and I've already committed the fix
separately.
> > I found as long as I avoid putting the <su> or <u> in the output template
> > (i.e. use an output statement instead of a template) it works. It only
> > seems to fail in the IEEE128 case, and not in the SFDF case. I will submit
> > a
> > bug report on it after this gets checked in, as it will be simpler to
> > provide
> > a patch that people can test.
>
> Thanks.
>
> > +(define_insn_and_split "fix<uns>_trunc<SFDF:mode><QHI:mode>2"
> > + [(set (match_operand:<QHI:MODE> 0 "gpc_reg_operand" "=wJ,wJwK,r")
> > + (any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wJ,wJwK,wa")))
> > + (clobber (match_scratch:SI 2 "=X,X,wi"))]
> > + "TARGET_DIRECT_MOVE"
> > + "@
> > + fctiw<u>z %0,%1
> > + xscvdp<su>xws %x0,%x1
>
> This one cannot work with the <su> definition above, for example.
>
> > +(define_insn "fix<uns>_<IEEE128:mode><SDI:mode>2_hw"
> > + [(set (match_operand:SDI 0 "altivec_register_operand" "=v")
> > + (any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
> > + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
> > +{
> > + return (<CODE> == UNSIGNED_FIX) ? "xscvqpu<wd>z %0,%1" : "xscvqps<wd>z
> > %0,%1";
> > +}
>
> And it may well be why you need this.
>
> Rest looks good :-)
Here is the patch reworked. It bootstraps on both little/big endian power8,
and all of the tests run. Can I install this into trunk now, and into GCC 7
after a soak period (along with the previous patch)?
[gcc]
2018-02-06 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/84154
* config/rs6000/rs6000.md (fix_trunc<SFDF:mode><QHI:mode>2):
Convert from define_expand to be define_insn_and_split. Rework
float/double/_Float128 conversions to QI/HI/SImode to work with
both ISA 2.07 (power8) or ISA 3.0 (power9). Fix regression where
conversions to QI/HImode types did a store and then a load to
truncate the value. For conversions to VSX registers, don't split
the insn, instead emit the code directly. Use the code iterator
any_fix to combine signed and unsigned conversions.
(fix<uns>_trunc<SFDF:mode>si2_p8): Likewise.
(fixuns_trunc<SFDF:mode><QHI:mode>2): Likewise.
(fix_trunc<IEEE128:mode><QHI:mode>2): Likewise.
(fix<uns>_trunc<SFDF:mode><QHI:mode>2): Likewise.
(fix_<mode>di2_hw): Likewise.
(fixuns_<mode>di2_hw): Likewise.
(fix_<mode>si2_hw): Likewise.
(fixuns_<mode>si2_hw): Likewise.
(fix<uns>_<IEEE128:mode><SDI:mode>2_hw): Likewise.
(fix<uns>_trunc<IEEE128:mode><QHI:mode>2): Likewise.
(fctiw<u>z_<mode>_smallint): Rename fctiw<u>z_<mode>_smallint to
fix<uns>_trunc<SFDF:mode>si2_p8.
(fix_trunc<SFDF:mode><QHI:mode>2_internal): Delete, no longer
used.
(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fix<uns>_<mode>_mem): Likewise.
(fctiw<u>z_<mode>_mem): Likewise.
(fix<uns>_<mode>_mem): Likewise.
(fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem): On ISA 3.0, prevent
the register allocator from doing a direct move to the GPRs to do
a store, and instead use the ISA 3.0 store byte/half-word from
vector register instruction. For IEEE 128-bit floating point,
also optimize stores of 32-bit ints.
(fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem): Likewise.
[gcc/testsuite]
2018-02-06 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/84154
* gcc.target/powerpc/pr84154-1.c: New tests.
* gcc.target/powerpc/pr84154-2.c: Likewise.
* gcc.target/powerpc/pr84154-3.c: Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 257269)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -5700,43 +5700,60 @@ (define_insn "*fix_trunc<mode>di2_fctidz
xscvdpsxds %x0,%x1"
[(set_attr "type" "fp")])
-(define_expand "fix_trunc<SFDF:mode><QHI:mode>2"
- [(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
- (fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
- (clobber (match_scratch:DI 2))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
+;; If have ISA 3.0, QI/HImode values can go in both VSX registers and GPR
+;; registers. If we have ISA 2.07, we don't allow QI/HImode values in the
+;; vector registers, so we need to do direct moves to the GPRs, but SImode
+;; values can go in VSX registers. Keeping the direct move part through
+;; register allocation prevents the register allocator from doing a direct move
+;; of the SImode value to a GPR, and then a store/load.
+(define_insn_and_split "fix<uns>_trunc<SFDF:mode><QHI:mode>2"
+ [(set (match_operand:<QHI:MODE> 0 "gpc_reg_operand" "=wJ,wJwK,r")
+ (any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wJ,wJwK,wa")))
+ (clobber (match_scratch:SI 2 "=X,X,wi"))]
+ "TARGET_DIRECT_MOVE"
+ "@
+ fctiw<u>z %0,%1
+ xscvdp<su>xws %x0,%x1
+ #"
+ "&& reload_completed && int_reg_operand (operands[0], <QHI:MODE>mode)"
+ [(set (match_dup 2)
+ (any_fix:SI (match_dup 1)))
+ (set (match_dup 3)
+ (match_dup 2))]
{
- if (MEM_P (operands[0]))
- operands[0] = rs6000_address_for_fpconvert (operands[0]);
-})
+ operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]));
+}
+ [(set_attr "length" "4,4,8")
+ (set_attr "type" "fp")])
+
+(define_insn "*fix<uns>_trunc<SFDF:mode>si2_p8"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=d,wa")
+ (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
+ "TARGET_DIRECT_MOVE"
+ "@
+ fctiw<u>z %0,%1
+ xscvdp<su>xws %x0,%x1"
+ [(set_attr "type" "fp")])
-(define_insn_and_split "*fix_trunc<SFDF:mode><QHI:mode>2_internal"
- [(set (match_operand:<QHI:MODE> 0 "reg_or_indexed_operand" "=wIwJ,rZ")
- (fix:QHI
- (match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
- (clobber (match_scratch:DI 2 "=X,wi"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
+;; Keep the convert and store together through register allocation to prevent
+;; the register allocator from getting clever and doing a direct move to a GPR
+;; and then store for reg+offset stores.
+(define_insn_and_split "*fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem"
+ [(set (match_operand:QHSI 0 "memory_operand" "=Z")
+ (any_fix:QHSI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
+ (clobber (match_scratch:SI 2 "=wa"))]
+ "((<QHSI:MODE>mode == SImode && TARGET_P8_VECTOR)
+ || (<QHSI:MODE>mode != SImode && TARGET_P9_VECTOR))"
"#"
"&& reload_completed"
- [(const_int 0)]
+ [(set (match_dup 2)
+ (any_fix:SI (match_dup 1)))
+ (set (match_dup 0)
+ (match_dup 3))]
{
- rtx dest = operands[0];
- rtx src = operands[1];
-
- if (vsx_register_operand (dest, <QHI:MODE>mode))
- {
- rtx di_dest = gen_rtx_REG (DImode, REGNO (dest));
- emit_insn (gen_fix_trunc<SFDF:mode>di2 (di_dest, src));
- }
- else
- {
- rtx tmp = operands[2];
- rtx tmp2 = gen_rtx_REG (<QHI:MODE>mode, REGNO (tmp));
-
- emit_insn (gen_fix_trunc<SFDF:mode>di2 (tmp, src));
- emit_move_insn (dest, tmp2);
- }
- DONE;
+ operands[3] = (<QHSI:MODE>mode == SImode
+ ? operands[2]
+ : gen_rtx_REG (<QHSI:MODE>mode, REGNO (operands[2])));
})
(define_expand "fixuns_trunc<mode>si2"
@@ -5803,71 +5820,6 @@ (define_insn "fixuns_trunc<mode>di2"
xscvdpuxds %x0,%x1"
[(set_attr "type" "fp")])
-(define_expand "fixuns_trunc<SFDF:mode><QHI:mode>2"
- [(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
- (unsigned_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
- (clobber (match_scratch:DI 2))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
-{
- if (MEM_P (operands[0]))
- operands[0] = rs6000_address_for_fpconvert (operands[0]);
-})
-
-(define_insn_and_split "*fixuns_trunc<SFDF:mode><QHI:mode>2_internal"
- [(set (match_operand:<QHI:MODE> 0 "reg_or_indexed_operand" "=wIwJ,rZ")
- (unsigned_fix:QHI
- (match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
- (clobber (match_scratch:DI 2 "=X,wi"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- rtx dest = operands[0];
- rtx src = operands[1];
-
- if (vsx_register_operand (dest, <QHI:MODE>mode))
- {
- rtx di_dest = gen_rtx_REG (DImode, REGNO (dest));
- emit_insn (gen_fixuns_trunc<SFDF:mode>di2 (di_dest, src));
- }
- else
- {
- rtx tmp = operands[2];
- rtx tmp2 = gen_rtx_REG (<QHI:MODE>mode, REGNO (tmp));
-
- emit_insn (gen_fixuns_trunc<SFDF:mode>di2 (tmp, src));
- emit_move_insn (dest, tmp2);
- }
- DONE;
-})
-
-;; If -mvsx-small-integer, we can represent the FIX operation directly. On
-;; older machines, we have to use an UNSPEC to produce a SImode and move it
-;; to another location, since SImode is not allowed in vector registers.
-(define_insn "*fctiw<u>z_<mode>_smallint"
- [(set (match_operand:SI 0 "vsx_register_operand" "=d,wi")
- (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
- "@
- fctiw<u>z %0,%1
- xscvdp<su>xws %x0,%x1"
- [(set_attr "type" "fp")])
-
-;; Combiner pattern to prevent moving the result of converting a floating point
-;; value to 32-bit integer to GPR in order to save it.
-(define_insn_and_split "*fctiw<u>z_<mode>_mem"
- [(set (match_operand:SI 0 "memory_operand" "=Z")
- (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
- (clobber (match_scratch:SI 2 "=wa"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
- "#"
- "&& reload_completed"
- [(set (match_dup 2)
- (any_fix:SI (match_dup 1)))
- (set (match_dup 0)
- (match_dup 2))])
-
;; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
;; rather than (set (subreg:SI (reg)) (fix:SI ...))
;; because the first makes it clear that operand 0 is not live
@@ -14362,49 +14314,45 @@ (define_insn_and_split "trunc<mode>sf2_h
(set_attr "length" "8")])
;; Conversion between IEEE 128-bit and integer types
-(define_insn "fix_<mode>di2_hw"
- [(set (match_operand:DI 0 "altivec_register_operand" "=v")
- (fix:DI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "xscvqpsdz %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
-(define_insn "fixuns_<mode>di2_hw"
- [(set (match_operand:DI 0 "altivec_register_operand" "=v")
- (unsigned_fix:DI (match_operand:IEEE128 1 "altivec_register_operand"
"v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "xscvqpudz %0,%1"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-(define_insn "fix_<mode>si2_hw"
- [(set (match_operand:SI 0 "altivec_register_operand" "=v")
- (fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "xscvqpswz %0,%1"
+;; The fix function for DImode and SImode was declared earlier as a
+;; define_expand. It calls into rs6000_expand_float128_convert if we don't
+;; have IEEE 128-bit hardware support. QImode and HImode are not provided
+;; unless we have the IEEE 128-bit hardware.
+;;
+;; Unlike the code for converting SFmode/DFmode to QImode/HImode, we don't have
+;; to provide a GPR target that used direct move and a conversion in the GPR
+;; which works around QImode/HImode not being allowed in vector registers in
+;; ISA 2.07 (power8).
+(define_insn "fix<uns>_<IEEE128:mode><SDI:mode>2_hw"
+ [(set (match_operand:SDI 0 "altivec_register_operand" "=v")
+ (any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
+ "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "xscvqp<su><wd>z %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
-(define_insn "fixuns_<mode>si2_hw"
- [(set (match_operand:SI 0 "altivec_register_operand" "=v")
- (unsigned_fix:SI (match_operand:IEEE128 1 "altivec_register_operand"
"v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "xscvqpuwz %0,%1"
+(define_insn "fix<uns>_trunc<IEEE128:mode><QHI:mode>2"
+ [(set (match_operand:QHI 0 "altivec_register_operand" "=v")
+ (any_fix:QHI
+ (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
+ "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "xscvqp<su>wz %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
-;; Combiner pattern to prevent moving the result of converting an IEEE 128-bit
-;; floating point value to 32-bit integer to GPR in order to save it.
-(define_insn_and_split "*fix<uns>_<mode>_mem"
- [(set (match_operand:SI 0 "memory_operand" "=Z")
- (any_fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v")))
- (clobber (match_scratch:SI 2 "=v"))]
+;; Combiner patterns to prevent moving the result of converting an IEEE 128-bit
+;; floating point value to 8/16/32-bit integer to GPR in order to save it.
+(define_insn_and_split "*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem"
+ [(set (match_operand:QHSI 0 "memory_operand" "=Z")
+ (any_fix:QHSI
+ (match_operand:IEEE128 1 "altivec_register_operand" "v")))
+ (clobber (match_scratch:QHSI 2 "=v"))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"#"
"&& reload_completed"
[(set (match_dup 2)
- (any_fix:SI (match_dup 1)))
+ (any_fix:QHSI (match_dup 1)))
(set (match_dup 0)
(match_dup 2))])
Index: gcc/testsuite/gcc.target/powerpc/pr84154-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr84154-1.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr84154-1.c (revision 0)
@@ -0,0 +1,55 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+/* PR target/84154. Make sure conversion to char/short does not generate a
+ store and a load on ISA 2.07 and newer systems. */
+
+unsigned char
+double_to_uc (double x)
+{
+ return x;
+}
+
+signed char
+double_to_sc (double x)
+{
+ return x;
+}
+
+unsigned short
+double_to_us (double x)
+{
+ return x;
+}
+
+short
+double_to_ss (double x)
+{
+ return x;
+}
+
+unsigned int
+double_to_ui (double x)
+{
+ return x;
+}
+
+int
+double_to_si (double x)
+{
+ return x;
+}
+
+/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mextsh\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mrlwinm\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlbz\M} } } */
+/* { dg-final { scan-assembler-not {\mlhz\M} } } */
+/* { dg-final { scan-assembler-not {\mlha\M} } } */
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+/* { dg-final { scan-assembler-not {\mstw\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/pr84154-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr84154-2.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr84154-2.c (revision 0)
@@ -0,0 +1,58 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+/* PR target/84154. Make sure on ISA 2.07 (power8) that we store the result of
+ a conversion to char/short using an offsettable address does not generate
+ direct moves for storing 32-bit integers, but does do a direct move for
+ 8/16-bit integers. */
+
+void
+double_to_uc (double x, unsigned char *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_sc (double x, signed char *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_us (double x, unsigned short *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_ss (double x, short *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_ui (double x, unsigned int *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_si (double x, int *p)
+{
+ p[3] = x;
+}
+
+/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstb\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msth\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlbz\M} } } */
+/* { dg-final { scan-assembler-not {\mlhz\M} } } */
+/* { dg-final { scan-assembler-not {\mlha\M} } } */
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+/* { dg-final { scan-assembler-not {\mstw\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/pr84154-3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr84154-3.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr84154-3.c (revision 0)
@@ -0,0 +1,60 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+/* PR target/84154. Make sure on ISA 3.0 we store the result of a conversion
+ to char/short using an offsettable address does not generate direct moves
+ for storing 8/16/32-bit integers. */
+
+void
+double_to_uc (double x, unsigned char *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_sc (double x, signed char *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_us (double x, unsigned short *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_ss (double x, short *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_ui (double x, unsigned int *p)
+{
+ p[3] = x;
+}
+
+void
+double_to_si (double x, int *p)
+{
+ p[3] = x;
+}
+
+/* { dg-final { scan-assembler-times {\maddi\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstxsibx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstxsihx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlbz\M} } } */
+/* { dg-final { scan-assembler-not {\mlhz\M} } } */
+/* { dg-final { scan-assembler-not {\mlha\M} } } */
+/* { dg-final { scan-assembler-not {\mmfvsrwz\M} } } */
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+/* { dg-final { scan-assembler-not {\mstw\M} } } */
+/* { dg-final { scan-assembler-not {\mstb\M} } } */
+/* { dg-final { scan-assembler-not {\msth\M} } } */
