From: Eric Botcazou <ebotca...@adacore.com>
Date: Wed, 12 Oct 2011 00:33:43 +0200
>> I see, so we can test the code generation in the testsuite even if the
>> compiler was built against an assembler without support for the
>> instructions.
>
> At least partially, yes.
>
>> But in such a case, I'm unsure if I understand why i386.exp needs
>> these tests at all. The presence of support for a particular i386
>> intrinsic is an implicit property of the gcc sources that these test
>> cases are a part of.
>>
>> If the tests are properly added only once the code to support the i386
>> intrinsic is added as well, the checks seem superfluous.
>
> The check is an _object_ check, for example:
...
> So the first category of tests will always be executed, whereas the latter
> two
> will only be executed if you have the binutils support.
Thanks a lot for explaining things.
I'm currently testing the following patch in various scenerios, I'm pretty
sure this is what you had in mind.
Any feedback is appreciated, thanks again Eric.
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 9c7cc56..fa790b3 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -850,7 +850,11 @@ sparc_option_override (void)
cpu = &cpu_table[(int) sparc_cpu_and_features];
target_flags &= ~cpu->disable;
- target_flags |= cpu->enable;
+ target_flags |= (cpu->enable
+#ifndef HAVE_AS_FMAF_HPC_VIS3
+ & ~(MASK_FMAF | MASK_VIS3)
+#endif
+ );
/* If -mfpu or -mno-fpu was explicitly used, don't override with
the processor default. */
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 0642ff2..669f106 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1871,10 +1871,6 @@ extern int sparc_indent_opcode;
#ifndef HAVE_AS_FMAF_HPC_VIS3
#define AS_NIAGARA3_FLAG "b"
-#undef TARGET_FMAF
-#define TARGET_FMAF 0
-#undef TARGET_VIS3
-#define TARGET_VIS3 0
#else
#define AS_NIAGARA3_FLAG "d"
#endif
diff --git a/gcc/testsuite/gcc.target/sparc/cmask.c
b/gcc/testsuite/gcc.target/sparc/cmask.c
index 989274c..b3168ec 100644
--- a/gcc/testsuite/gcc.target/sparc/cmask.c
+++ b/gcc/testsuite/gcc.target/sparc/cmask.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { vis3 } } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
void test_cm8 (long x)
diff --git a/gcc/testsuite/gcc.target/sparc/fhalve.c
b/gcc/testsuite/gcc.target/sparc/fhalve.c
index 737fc71..340b936 100644
--- a/gcc/testsuite/gcc.target/sparc/fhalve.c
+++ b/gcc/testsuite/gcc.target/sparc/fhalve.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { vis3 } } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
float test_fhadds (float x, float y)
diff --git a/gcc/testsuite/gcc.target/sparc/fnegop.c
b/gcc/testsuite/gcc.target/sparc/fnegop.c
index 3e3e72c..25f8c19 100644
--- a/gcc/testsuite/gcc.target/sparc/fnegop.c
+++ b/gcc/testsuite/gcc.target/sparc/fnegop.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { vis3 } } } */
+/* { dg-do compile } */
/* { dg-options "-O2 -mcpu=niagara3 -mvis" } */
float test_fnadds(float x, float y)
diff --git a/gcc/testsuite/gcc.target/sparc/fpadds.c
b/gcc/testsuite/gcc.target/sparc/fpadds.c
index f55cb05..d0704e0 100644
--- a/gcc/testsuite/gcc.target/sparc/fpadds.c
+++ b/gcc/testsuite/gcc.target/sparc/fpadds.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { vis3 } } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef int __v2si __attribute__((vector_size(8)));
typedef int __v1si __attribute__((vector_size(4)));
diff --git a/gcc/testsuite/gcc.target/sparc/fshift.c
b/gcc/testsuite/gcc.target/sparc/fshift.c
index 6adbed6..a12df04 100644
--- a/gcc/testsuite/gcc.target/sparc/fshift.c
+++ b/gcc/testsuite/gcc.target/sparc/fshift.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { vis3 } } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef int __v2si __attribute__((vector_size(8)));
typedef short __v4hi __attribute__((vector_size(8)));
diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c
b/gcc/testsuite/gcc.target/sparc/fucmp.c
index 4e7ecad..7f291c3 100644
--- a/gcc/testsuite/gcc.target/sparc/fucmp.c
+++ b/gcc/testsuite/gcc.target/sparc/fucmp.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { vis3 } } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef unsigned char vec8 __attribute__((vector_size(8)));
diff --git a/gcc/testsuite/gcc.target/sparc/lzd.c
b/gcc/testsuite/gcc.target/sparc/lzd.c
index 5ffaf56..a897829 100644
--- a/gcc/testsuite/gcc.target/sparc/lzd.c
+++ b/gcc/testsuite/gcc.target/sparc/lzd.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { vis3 } } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=niagara3" } */
int test_clz(int a)
{
diff --git a/gcc/testsuite/gcc.target/sparc/vis3misc.c
b/gcc/testsuite/gcc.target/sparc/vis3misc.c
index e3ef49e..8a9535e 100644
--- a/gcc/testsuite/gcc.target/sparc/vis3misc.c
+++ b/gcc/testsuite/gcc.target/sparc/vis3misc.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { vis3 } } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef int __v2si __attribute__((vector_size(8)));
typedef short __v4hi __attribute__((vector_size(8)));
diff --git a/gcc/testsuite/gcc.target/sparc/xmul.c
b/gcc/testsuite/gcc.target/sparc/xmul.c
index 5d249d0..ce80e6c 100644
--- a/gcc/testsuite/gcc.target/sparc/xmul.c
+++ b/gcc/testsuite/gcc.target/sparc/xmul.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { vis3 } } } */
+/* { dg-do compile } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef long long int64_t;
