The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
0ceaec1e3c20... RISC-V: Read extension data from riscv-ext*.def for arch-ca
It previously pointed to:
d44bf7845e51... RISC-V: Read extension data from riscv-ext*.def for arch-ca
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
-------------------------------------------------------------------
d44bf78... RISC-V: Read extension data from riscv-ext*.def for arch-ca
2f09758... RISC-V: Support -march=unset
1a817b2... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
1fa89bf... RISC-V: Add testcases for signed avg ceil vx combine
455b485... RISC-V: Adding H to the canonical order [PR121312]
238146d... RISC-V: Add testcases for unsigned avg ceil vx combine.
3e13671... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
476b623... RISC-V: Remove use of structured binding to fix compiler wa
654e184... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
3868935... RISC-V: Add test case for vaadd.vx combine polluting VXRM
8b94f2e... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
00269a6... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
0ad7495... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
20463ef... RISC-V: Fix another vf FP16 combine run test failures
68f3bc7... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
cc3e882... RISC-V: Prepare dynamic LMUL heuristic for SLP.
848b7d7... RISC-V: Remove user-level interrupts
186ee4f... RISC-V: Add support for resumable non-maskable interrupt (R
3b9bc97... riscv: testsuite: Fix misalignment check.
a92f597... RISC-V: Add test case for vx combine polluting VXRM
3cdb452... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
313b3fe... RISC-V: Rework broadcast handling [PR121073].
ca0f045... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
763de94... Change bellow in comments to below
0bdb4d4... [RISC-V] Restrict generic-vector-ooo DFA
bf08d63... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
08c2796... [RISC-V] Fix wrong CFA during stack probe
69057e8... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
5b8472a... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
324e9a9... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
26e7498... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
93c2fcd... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
833cce5... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
c4c34c8... RISC-V: Refine the test case for vector avg_floor and avg_c
3a87484... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
e077fe0... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
4ea7601... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
8b53c83... RISC-V: Support RVVDImode for avg3_ceil auto vect
820f9d5... RISC-V: Fix vsetvl merge rule.
b8bea84... RISC-V: Refine the scalar SAT_* test cases
42743b8... RISC-V: Support RVVDImode for avg3_floor auto vect
83974e4... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
facb0b8... RISC-V: Add testcase for rv32 SAT_MUL from uint64
e0bc128... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
866b659... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
8d827db... RISC-V: Make zero-stride load broadcast a tunable.
635ac77... [RISC-V] Detect new fusions for RISC-V
20fcd8a... RISCV: Remove the v extension requirement for sat scalar ru
3ca3c6d... RISC-V: Add test for vec_duplicate + vssub.vv combine case
0934c87... RISC-V: Add test for vec_duplicate + vssub.vv combine case
a4c8e28... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
c5a3303... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
5d6fd53... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
b8558ce... [RISC-V][PR target/120642] Avoid propagating constant AVL f
e1b3e2b... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
d985f7a... RISC-V: Do not use vsetivli for THeadVector.
94db940... RISC-V: Ignore non-types in builtin function hash.
eddfc55... [committed][RISC-V] Fix testsuite fallout from check-functi
57b108b... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
04628a1... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
2ba4718... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
a82205f... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
9521224... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
342e0f6... [RISC-V] Add basic instrumentation to fusion detection
ed2c972... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
0190716... Refactor record_function_versions.
b8613cb... [RISC-V][PR target/118886] Refine when two insns are signal
ee451a0... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
17f6b67... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
7a4c77b... [RISC-V] Correct CFA notes for stack-clash protection [PR12
631cf6b... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
5086e8b... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
e33555b... RISC-V: Reconcile the existing test due to cost model chang
2e78bb2... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
d1ec2e5... RISC-V: Ignore -Oz for most rvv testcase [NFC]
6b0f5fe... RISC-V: Primary vector pipeline model for sifive 7 series
d9f0595... RISC-V: Adding B ext, fp16 and missing scalar instruction t
2b19c58... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
85765e5... RISC-V: Refactor the function bitmap_union_of_preds_with_en
fba8b6e... RISC-V: Add pipeline-checker script
00fac0b... [sanitizer_common] Fix build on ppc64+musl (#120036)
310914d... [RISC-V][PR target/119971] Avoid losing shift count masking
468cffa... RISC-V: update prepare_ternary_operands to handle vector-sc
7bef4a4... RISC-V: Fix build issue
21a280f... RISC-V: Add comment and reorder the the include files in ri
ed0e22e... RISC-V: Add Profiles RVA/B23S64 support.
38505ba... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
6521311... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
786c243... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
e3cb2ec... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
7d12abe... [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit host
cef5e1c... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
dcdaa59... RISC-V: Fix ICE for expand_select_vldi [PR120652]
ba2759d... [RISC-V] Force several tests to use rocket tuning
2abb0cc... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
dced81d... RISC-V: Add test for vec_duplicate + vminu.vv combine case
6374a66... RISC-V: Add test for vec_duplicate + vminu.vv combine case
0e4f34c... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
5fb7812... RISC-V: Add generic tune as default.
266be98... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
786c105... RISC-V: Adding cost model for zilsd
a82b84b... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
70cb9df... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
df78e45... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
4dd8fe7... [PATCH v1] RISC-V: Use scratch reg for loop control
7fd0df1... RISC-V: Add -fno-pie flags to testcases
6c5006c... RISC-V: Refine VX combine test case 0 to avoid code duplica
8490803... RISC-V: Update Profiles string in RV23.
7ed9776... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
6a37b4b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
73635d8... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
8c01d04... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
0960d4b... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
64fc9a9... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
9ae4084... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
97a13af... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
7cea665... RISC-V: Prevent speculative vsetvl insn scheduling
0f9e3fb... RISC-V: Add patterns for vector-scalar negate-(multiply-add
055b964... RISC-V: testsuite: fix an obvious build error
318ee82... RISC-V: Regen riscv-ext.texi [NFC]
e54ba9f... RISC-V: Add test for vec_duplicate + vremu.vv combine case
352cd26... RISC-V: Add test for vec_duplicate + vremu.vv combine case
c948a9f... RISC-V: Reconcile the existing test for vremu.vx combine
a905f01... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
42038b7... [RISC-V] Enable more if-conversion on RISC-V
2ed33da... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
115afc1... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
579ff53... RISC-V: Reconcile the existing test for vrem.vx combine
937fc54... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
5820ee6... RISC-V: frm/mode-switch: robustify call_insn backtracking [
d3e584d... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
82333ed... RISC-V: frm/mode-switch: remove dubious frm edge insertion
9f72bfe... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
b6a2b75... [RISC-V] Handle 32bit operands in condition for conditional
f86dd7d... [to-be-committed][RISC-V] Handle 32bit operands in conditio
9c4f680... RISC-V: Reconcile the existing test for vdivu.vx combine
48668f8... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
2a2b2fa... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
d1d5fdf... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
3daa678... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
680eb45... [RISC-V] Improve signed division by 2^n
772f741... RISC-V: Don't use structured binding in riscv-common.cc
358e3e7... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
38649b2... [RISC-V] Improve sequences to generate -1, 1 in some cases.
d0b4acf... RISC-V: Support Ssu64xl extension.
9a07898... RISC-V: Support Sstvecd extension.
48a5024... RISC-V: Support Sstvala extension.
dd2ede7... RISC-V: Support Sscounterenw extension.
ccdbacd... RISC-V: Support Ssccptr extension.
0900666... RISC-V: Support Smrnmi extension.
fcf5184... RISC-V: Support Sm/scsrind extensions.
7be775b... RISC-V: Update extension defination.
259286d... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
2b27d40... [PATCH v2] RISC-V: Add svbare extension.
7f77969... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
2fbcc82... RISC-V: Add Shlcofideleg extension.
da9ec3b... RISC-V: Reconcile the existing test for vdiv.vx combine
e69c82d... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
d6292a3... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
c46ca69... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
5683360... RISC-V: Use helper function to get FPR to VR move cost
19dbe09... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
f1d4078... [PATCH] RISC-V: Add smcntrpmf extension.
e785b6c... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
55eb9e7... RISC-V: Implement full-featured iterator for riscv_subset_l
d4558db... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
f974122... RISC-V: Fix line too long format issue for autovect.md [NFC
1ee144c... RISC-V: Add test cases for avg_ceil vaadd implementation
f2fac47... RISC-V: Reconcile the existing test for avg_ceil
4b90529... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
bcc01ae... RISC-V: Add minimal support of double trap extension 1.0
925b08e... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
602c779... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
325bc4d... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
471c5ca... RISC-V: Avoid division by zero in check_builtin_call [PR120
28f5689... RISC-V: Add test cases for avg_floor vaadd implementation
531ba01... RISC-V: Reconcile the existing test for avg_floor
db8d20c... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
b81f4e6... [RISC-V] Add andi+bclr synthesis
7e355a1... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
379a1e8... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
1176178... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
443544e... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
5d4ed37... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
7b9c940... [RISC-V] shift+and+shift for logical and synthesis
2cb7dfe... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
9bb6cb1... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
c3ccaeb... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
d623e56... RISC-V: Support CPUs in -march.
d945530... RISC-V: Add autovec mode param.
d70217b... RISC-V: Default-initialize variable.
07c935e... RISC-V: Fix some dynamic LMUL costing.
86e3149... [RISC-V] Clear both upper and lower bits using 3 shifts
e9fcf56... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
ff8ae1f... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
e168199... [RISC-V] Clear high or low bits using shift pairs
1800970... [RISC-V] Improve (x << C1) + C2 split code
22afab2... [RISC-V][PR target/120368] Fix 32bit shift on rv64
a031409... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
b29ef1d... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
bbf2554... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
db7b07b... [RISC-V] Infrastructure of synthesizing logical AND with co
7fc9ea3... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
a299c80... [PATCH v2 1/2] The following changes enable P8700 processor
9a12ab9... [RISC-V] Avoid multiple assignments to output object
3f02e70... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
63d4c14... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
79af32b... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
a61bdc6... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
eab2ec4... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
9fa6927... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
0c11523... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
fc82eb2... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
99ec4f5... [committed][RISC-V][PR target/120333] Remove bogus bext pat
091ab94... [RISC-V] Fix false positive from Wuninitialized
1e14441... RISC-V: Fix the warning of temporary object dangling refere
6f72204... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
461df40... RISC-V: Support Zilsd code gen
cd7a452... RISC-V: Add new operand constraint: cR
b65055e... [RISC-V] Fix ICE due to bogus use of gen_rtvec
e8fa4f5... [RISC-V] Avoid setting output object more than once in IOR/
451b730... RISC-V: Since the loop increment i++ is unreachable, the lo
8bf87f6... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
3895fb9... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
29efbaf... Make end_sequence return the insn sequence
db7d25f... RISC-V: Reuse test name for vx combine test data [NFC]
c0013e0... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
e0f154c... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
1f05f3d... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
ede937e... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
aaf3bbc... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
af21cd7... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
b96371d... RISC-V: Adjust vx combine test case to avoid name conflict
c382fb4... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
bf8f136... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
d9249d2... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
2e8b43b... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
c76dafe... RISC-V: Add augmented hypervisor series extensions.
79a7b67... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
50aaf5d... RISC-V: Regen riscv-ext.opt.urls
3bc9532... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
ff81339... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
de2de27... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
eac0419... RISC-V: Introduce riscv_ext_info_t to hold extension metada
fcadee7... RISC-V: Adjust riscv_can_inline_p
5a3297a... RISC-V: Generate extension table in documentation from risc
426bc13... RISC-V: Use riscv-ext.def to generate target options and va
33320cb... RISC-V: Introduce riscv-ext*.def to define extensions
dc93659... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
6fa627e... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
0a3c888... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
5104390... RISC-V: Support for zilsd and zclsd extensions.
bb3f52e... testsuite: Fix RISC-V arch-52.c format issue.
f08ba94... RISC-V: Support RISC-V Profiles 23.
f2e5a82... RISC-V: Support RISC-V Profiles 20/22.
cd47f8d... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
85998f2... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
9fb73d6... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
d334d95... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
1c01c23... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
32ad857... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
6cb8d32... RISC-V: Separate the test running of rvv vx_vf
83782c5... [RISC-V][PR target/120137][PR target/120154] Don't create o
0062d6a... [PATCH] RISC-V: Minimal support for zama16b extension.
5408f5d... [RISC-V] Avoid unnecessary andi with -1 argument
91c7828... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
39c180d... [PATCH] RISC-V: Recognized svadu and svade extension
7508d78... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
8f30e58... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
8cfb089... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
3a7248f... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
3d37606... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
6d876dd... RISC-V: Add gr2vr cost helper function
467cd89... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
e899499... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
2bd9a08... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
70a3a1e... [V2][RISC-V] Trivial permutation constant derivation
03cdf8a... [RISC-V] Adjust rvv tests after recent jump threading chang
9090b44... [PATCH] RISC-V: Implment H modifier for printing the next r
3051776... [to-be-committed][RISC-V] Adjust testcases and finish regis
c4243db... RISC-V: Remove unnecessary frm restore volatile define_insn
94418d3... RISC-V: Allow different dynamic floating point mode to be m
8e26f37... RISC-V: Fix missing implied Zicsr from Zve32x
eea8d50... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
2f3f601... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
6675719... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
4077ce6... RISC-V: Extract vector stepped for expand_const_vector [NFC
c7b18d2... RISC-V: Extract vector duplicate for expand_const_vector [N
7bc3d61... RISC-V: Extract vec_series for expand_const_vector [NFC]
de604dd... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
12dcf63... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
d3c54b6... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
d3bc131... [riscv] vec_dup immediate constants in pred_broadcast expan
2b051e8... [RISC-V][PR target/119865] Don't free ggc allocated memory
8f90305... [RISC-V][PR target/118410] Improve code generation for some
3dec414... [RISC-V] Fix missed bext discovery
519ab56... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
ac7a631... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
132f778... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
Summary of changes (added commits):
-----------------------------------
0ceaec1... RISC-V: Read extension data from riscv-ext*.def for arch-ca
5ab4a75... RISC-V: Support -march=unset
e479452... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
52b5390... RISC-V: Add testcases for signed avg ceil vx combine
f6a6b35... RISC-V: Adding H to the canonical order [PR121312]
d848d8f... RISC-V: Add testcases for unsigned avg ceil vx combine.
b5bfad9... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
30259f6... RISC-V: Remove use of structured binding to fix compiler wa
5e1b602... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
99e0eab... RISC-V: Add test case for vaadd.vx combine polluting VXRM
db17589... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
573df94... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
6ed7331... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
d7386b2... RISC-V: Fix another vf FP16 combine run test failures
0e62026... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
253df77... RISC-V: Prepare dynamic LMUL heuristic for SLP.
c66e78e... RISC-V: Remove user-level interrupts
a456482... RISC-V: Add support for resumable non-maskable interrupt (R
c8e57bc... riscv: testsuite: Fix misalignment check.
68fdfa9... RISC-V: Add test case for vx combine polluting VXRM
4e0e71d... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
e59fca8... RISC-V: Rework broadcast handling [PR121073].
3045d93... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
7f0f699... Change bellow in comments to below
de873d0... [RISC-V] Restrict generic-vector-ooo DFA
8e2532b... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
625dba4... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
85bab69... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
9c72d92... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
7300f3c... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
9be4e27... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
c3e31ff... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
4e0886f... RISC-V: Refine the test case for vector avg_floor and avg_c
4c810e2... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
1ef04f1... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
45a9ae5... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
86afee5... RISC-V: Support RVVDImode for avg3_ceil auto vect
568d5f2... RISC-V: Fix vsetvl merge rule.
394c4f0... RISC-V: Refine the scalar SAT_* test cases
6e7869a... RISC-V: Support RVVDImode for avg3_floor auto vect
978dc34... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
48a48de... RISC-V: Add testcase for rv32 SAT_MUL from uint64
dc15a0c... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
2f74422... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
e12eda6... RISC-V: Make zero-stride load broadcast a tunable.
566bdaf... [RISC-V] Detect new fusions for RISC-V
13eb068... RISCV: Remove the v extension requirement for sat scalar ru
ff641fe... RISC-V: Add test for vec_duplicate + vssub.vv combine case
ad153da... RISC-V: Add test for vec_duplicate + vssub.vv combine case
c7336b0... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
2bf583a... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
c26128c... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
063463c... [RISC-V][PR target/120642] Avoid propagating constant AVL f
551a107... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
cc172c4... RISC-V: Do not use vsetivli for THeadVector.
cee886d... RISC-V: Ignore non-types in builtin function hash.
70ef784... [committed][RISC-V] Fix testsuite fallout from check-functi
c2407a3... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
f350a0c... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
dd13f63... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
9a7ef48... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
7adca55... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
34058e1... [RISC-V] Add basic instrumentation to fusion detection
564db69... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
6178f49... Refactor record_function_versions.
93272b7... [RISC-V][PR target/118886] Refine when two insns are signal
334c22f... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
b86b8dc... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
356827b... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
0077e94... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
f72695c... RISC-V: Reconcile the existing test due to cost model chang
2fddfd4... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
ad0f9e6... RISC-V: Ignore -Oz for most rvv testcase [NFC]
e0b6c51... RISC-V: Primary vector pipeline model for sifive 7 series
13c275d... RISC-V: Adding B ext, fp16 and missing scalar instruction t
3de8682... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
d62850c... RISC-V: Refactor the function bitmap_union_of_preds_with_en
03d4fda... RISC-V: Add pipeline-checker script
cb2c306... [RISC-V][PR target/119971] Avoid losing shift count masking
f7e693e... RISC-V: update prepare_ternary_operands to handle vector-sc
3293115... RISC-V: Fix build issue
436ca61... RISC-V: Add comment and reorder the the include files in ri
9a60d90... RISC-V: Add Profiles RVA/B23S64 support.
32287cd... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
d0a15c3... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
ea9b5ca... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
906d69a... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
56209be... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
9c6c2f8... RISC-V: Fix ICE for expand_select_vldi [PR120652]
d180109... [RISC-V] Force several tests to use rocket tuning
d53c9b2... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
4dee717... RISC-V: Add test for vec_duplicate + vminu.vv combine case
5dfc31e... RISC-V: Add test for vec_duplicate + vminu.vv combine case
c05b45d... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
3cfa6a2... RISC-V: Add generic tune as default.
5bf0e9c... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
fd09081... RISC-V: Adding cost model for zilsd
4e64890... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
1e807de... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
050c187... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
f963497... [PATCH v1] RISC-V: Use scratch reg for loop control
ccfe26a... RISC-V: Add -fno-pie flags to testcases
65d1ac5... RISC-V: Refine VX combine test case 0 to avoid code duplica
86be89c... RISC-V: Update Profiles string in RV23.
4f3afc8... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
a8251d8... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
0f96892... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
28933a9... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
90a723a... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
ba5f5cd... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
a197167... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
2dccc3c... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
285565e... RISC-V: Prevent speculative vsetvl insn scheduling
5a03517... RISC-V: Add patterns for vector-scalar negate-(multiply-add
683f824... RISC-V: testsuite: fix an obvious build error
ebf330e... RISC-V: Regen riscv-ext.texi [NFC]
3377320... RISC-V: Add test for vec_duplicate + vremu.vv combine case
3b6fa01... RISC-V: Add test for vec_duplicate + vremu.vv combine case
0882060... RISC-V: Reconcile the existing test for vremu.vx combine
0a22c4e... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
29a33cd... [RISC-V] Enable more if-conversion on RISC-V
526b314... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
e0f49ad... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
1b8f4c8... RISC-V: Reconcile the existing test for vrem.vx combine
ff9dd59... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
4537df1... RISC-V: frm/mode-switch: robustify call_insn backtracking [
60bc461... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
ab2296a... RISC-V: frm/mode-switch: remove dubious frm edge insertion
afa3a29... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
48c0e1b... [RISC-V] Handle 32bit operands in condition for conditional
4570b7a... [to-be-committed][RISC-V] Handle 32bit operands in conditio
b29f1a5... RISC-V: Reconcile the existing test for vdivu.vx combine
b86c248... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
266995f... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
a379634... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
3df1dc7... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
e1d2a08... [RISC-V] Improve signed division by 2^n
4292398... RISC-V: Don't use structured binding in riscv-common.cc
14ae4fc... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
27276d0... [RISC-V] Improve sequences to generate -1, 1 in some cases.
74234c1... RISC-V: Support Ssu64xl extension.
513e440... RISC-V: Support Sstvecd extension.
2ea363d... RISC-V: Support Sstvala extension.
564ebab... RISC-V: Support Sscounterenw extension.
4bf2cba... RISC-V: Support Ssccptr extension.
1cd8ae2... RISC-V: Support Smrnmi extension.
3b48b27... RISC-V: Support Sm/scsrind extensions.
a7ff487... RISC-V: Update extension defination.
72a0edb... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
018cbeb... [PATCH v2] RISC-V: Add svbare extension.
1aee963... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
c704372... RISC-V: Add Shlcofideleg extension.
b8733d0... RISC-V: Reconcile the existing test for vdiv.vx combine
2071bce... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
b0cdf75... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
a4dac5a... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
1bb8daa... RISC-V: Use helper function to get FPR to VR move cost
768a4e6... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
0ede5d6... [PATCH] RISC-V: Add smcntrpmf extension.
f7f08b1... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
1c7d9a9... RISC-V: Implement full-featured iterator for riscv_subset_l
724c9b6... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
8eae88c... RISC-V: Fix line too long format issue for autovect.md [NFC
8459e82... RISC-V: Add test cases for avg_ceil vaadd implementation
2d908d4... RISC-V: Reconcile the existing test for avg_ceil
d8605e9... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
e5f20d8... RISC-V: Add minimal support of double trap extension 1.0
f5cbc6c... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
35ec150... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
1b0fdf1... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
4c46bf1... RISC-V: Avoid division by zero in check_builtin_call [PR120
2467c5e... RISC-V: Add test cases for avg_floor vaadd implementation
66bdf07... RISC-V: Reconcile the existing test for avg_floor
b95528e... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
8b4ca30... [RISC-V] Add andi+bclr synthesis
29d9596... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
1eb825b... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
25636a5... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
db7dfcc... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
05dd345... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
0a9f987... [RISC-V] shift+and+shift for logical and synthesis
d631d0d... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
60e1c46... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
664e586... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
6a958e2... RISC-V: Support CPUs in -march.
35c4531... RISC-V: Add autovec mode param.
ca87230... RISC-V: Default-initialize variable.
c4e3800... RISC-V: Fix some dynamic LMUL costing.
06366b6... [RISC-V] Clear both upper and lower bits using 3 shifts
eed4db2... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
e070b74... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
467e2cd... [RISC-V] Clear high or low bits using shift pairs
0d78e88... [RISC-V] Improve (x << C1) + C2 split code
19d46c3... [RISC-V][PR target/120368] Fix 32bit shift on rv64
36a891e... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
ada0aeb... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
ce5b307... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
466a427... [RISC-V] Infrastructure of synthesizing logical AND with co
bcb5a63... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
f82d216... [PATCH v2 1/2] The following changes enable P8700 processor
de1cd61... [RISC-V] Avoid multiple assignments to output object
5a5b821... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
989006f... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
7f95c42... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
273ecfc... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
90e18e5... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
03d050b... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
5138074... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
46b9773... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
a958028... [committed][RISC-V][PR target/120333] Remove bogus bext pat
64ded69... [RISC-V] Fix false positive from Wuninitialized
2dc5d10... RISC-V: Fix the warning of temporary object dangling refere
5e04e21... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
8aa934f... RISC-V: Support Zilsd code gen
1a4622c... RISC-V: Add new operand constraint: cR
05d676f... [RISC-V] Fix ICE due to bogus use of gen_rtvec
2214931... [RISC-V] Avoid setting output object more than once in IOR/
578b489... RISC-V: Since the loop increment i++ is unreachable, the lo
954ec1b... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
15f1b47... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
8108407... Make end_sequence return the insn sequence
6fb0a11... RISC-V: Reuse test name for vx combine test data [NFC]
b9d2b65... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
2040241... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
6ee8db8... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
6be74a7... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
4c149d5... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
bf30abb... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
cd34725... RISC-V: Adjust vx combine test case to avoid name conflict
00e7995... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
5d7d08f... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
8942f00... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
a709ba0... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
1f141db... RISC-V: Add augmented hypervisor series extensions.
e3f0e28... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
7c5a6c4... RISC-V: Regen riscv-ext.opt.urls
484779e... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
8393c6e... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
8eb93eb... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
08ab8be... RISC-V: Introduce riscv_ext_info_t to hold extension metada
5d12c14... RISC-V: Adjust riscv_can_inline_p
efeece8... RISC-V: Generate extension table in documentation from risc
9b3b616... RISC-V: Use riscv-ext.def to generate target options and va
7bf2bae... RISC-V: Introduce riscv-ext*.def to define extensions
96bf160... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
54a8f57... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
26d0222... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
e8a1d6c... RISC-V: Support for zilsd and zclsd extensions.
eae901d... testsuite: Fix RISC-V arch-52.c format issue.
109cbec... RISC-V: Support RISC-V Profiles 23.
1db0ba3... RISC-V: Support RISC-V Profiles 20/22.
d2317a4... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
3d2c2d7... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
761cda3... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
15c0407... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
cfac397... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
138dad5... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
b39fe64... RISC-V: Separate the test running of rvv vx_vf
cb158e9... [RISC-V][PR target/120137][PR target/120154] Don't create o
f2f4abc... [PATCH] RISC-V: Minimal support for zama16b extension.
bc3cfb5... [RISC-V] Avoid unnecessary andi with -1 argument
1f4c76e... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
c8ff9f6... [PATCH] RISC-V: Recognized svadu and svade extension
25156b3... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
6ce6856... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
8299b07... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
db56a68... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
c8c8adc... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
5a62e23... RISC-V: Add gr2vr cost helper function
bdf2f69... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
04814f5... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
bd8634d... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
ec33d8e... [V2][RISC-V] Trivial permutation constant derivation
f018d3d... [RISC-V] Adjust rvv tests after recent jump threading chang
dd57a86... [PATCH] RISC-V: Implment H modifier for printing the next r
73ffb70... [to-be-committed][RISC-V] Adjust testcases and finish regis
6616880... RISC-V: Remove unnecessary frm restore volatile define_insn
f8d5ad6... RISC-V: Allow different dynamic floating point mode to be m
e2c27df... RISC-V: Fix missing implied Zicsr from Zve32x
0bddf83... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
40cfb6a... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
2582fd1... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
4dd3e80... RISC-V: Extract vector stepped for expand_const_vector [NFC
213bb02... RISC-V: Extract vector duplicate for expand_const_vector [N
1da5604... RISC-V: Extract vec_series for expand_const_vector [NFC]
70f9b3e... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
7bac648... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
3d75b40... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
91f7009... [riscv] vec_dup immediate constants in pred_broadcast expan
a17f68d... [RISC-V][PR target/119865] Don't free ggc allocated memory
36af932... [RISC-V][PR target/118410] Improve code generation for some
c7a48ec... [RISC-V] Fix missed bext discovery
6eaa359... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
a4d3a49... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
8db08e9... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
1276b39... LoongArch: Fix ICE in highway-1.3.0 testsuite [PR121634] (*)
c83bccb... Daily bump. (*)
49b35bd... Update gcc de.po (*)
718ee28... Daily bump. (*)
0c409bc... Daily bump. (*)
8795005... RTEMS: Add riscv multilibs (*)
5bbc82d... Daily bump. (*)
be4d95d... Daily bump. (*)
f8c8edf... AVR: target/121608 - Don't add --relax when linking with -r (*)
f12a272... RISC-V: fix __builtin_round clobbering FP exceptions flags (*)
4fc8d0d... Daily bump. (*)
334324b... libstdc++: Fix-self element self-assigments when inserting (*)
3fb3441... libstdc++: Do not expose set_brackets/set_separator for for (*)
9e00f7c... testsuite: Fix PR108080 testcase for some targets [PR121396 (*)
62d800e... Daily bump. (*)
ed47725... aarch64: libgcc: Honor disable-werror [PR117600] (*)
58a9717... aarch64: Fix mode mismatch when building a predicate [PR121 (*)
47cdd87... fwprop: Don't propagate asms [PR121253] (*)
f9de142... Daily bump. (*)
62bae71... Daily bump. (*)
828eb1b... Daily bump. (*)
9fe46a4... aarch64: Relax fpm_t assert to allow const_ints [PR120986] (*)
0abf53c... aarch64: Fix predication of FP8 FDOT insns [PR120986] (*)
17eae3d... AArch64: Fix invalid immediate offsets in SVE gather/scatte (*)
27d6b60... LoongArch: Fix ICE caused by function add_stmt_cost[PR12154 (*)
2c28b41... Daily bump. (*)
868a577... aarch64: Mark SME functions as .variant_pcs [PR121414] (*)
701193a... aarch64: Use VNx16BI for svrev_b* [PR121294] (*)
4cf9d4e... aarch64: Use VNx16BI for more permutations [PR121294] (*)
d755aa0... Remove MODE_COMPOSITE_P test from simplify_gen_subreg [PR12 (*)
ef1bd81... [PR121007, LRA]: Fall back to reload of whole inner address (*)
1694cba... [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit host (*)
e5905a5... x86: Pass -mno-80387 to compile pr121208-1(a|b).c (*)
afd88fa... x86: Disallow -mtls-dialect=gnu with no_caller_saved_regist (*)
f745d12... Daily bump. (*)
5c099ee... aarch64: Adapt unwinder to linux's SME signal behaviour (*)
c4e96a0... LoongArch: Define hook TARGET_COMPUTE_PRESSURE_CLASSES[PR12 (*)
b078015... Fortran: Fix runtime bogus diagnostic with ';' (*)
88091b1... Daily bump. (*)
76aeacb... LoongArch: macro instead enum for base abi type (*)
aa8151d... Daily bump. (*)
da49190... Update gcc .po files (*)
98b34b5... [testsuite] add missing require vect_early_break_hw for vec (*)
b7b7a2c... Daily bump. (*)
ad63c0b... testsuite: i386: Fix gcc.target/i386/pr90579.c when PIE is (*)
4521236... testsuite: handle-multiline-outputs must allow both cc1 and (*)
21a87ad... lra: Reallow reloading user hard registers if the insn is n (*)
06f43df... testsuite: Enable the PR 87600 tests for LoongArch (*)
917956f... Daily bump. (*)
929da38... Daily bump. (*)
9faa21a... c++: constrained memfn vs corresponding using [PR121351] (*)
b389343... c++: constexpr evaluation of abi::__dynamic_cast [PR120620] (*)
d3c5366... tailc: Handle other forms of finally_tmp.N conditional clea (*)
d43ece3... bitint: Fix up INTEGER_CST PHI handling [PR121413] (*)
332e891... bitint: Fix up handling of uninitialized mul/div/float cast (*)
a88f4ef... libstdc++: Add various missing exports [PR121373] (*)
8193500... libcpp: Fix up cpp_maybe_module_directive [PR120845] (*)
47dd300... Bump BASE-VER (*)
5115c7e... Update ChangeLog and version files for release (*)
46deccf... Daily bump. (*)
921c1ce... libgomp.texi: Document omp(x)::allocator::*, restructure me (*)
267411c... i386: Fix invalid RTX mode in the unnamed rotate splitter. (*)
059889c... Daily bump. (*)
3f89850... AArch64: Fix test for vector length safety (*)
810fd78... Daily bump. (*)
bf1dff1... Daily bump. (*)
b7175db... Daily bump. (*)
4c7b58d... Daily bump. (*)
7b56621... Daily bump. (*)
08f9328... Regenerate gcc.pot (*)
e14a895... arm: fully validate mem_noofs_operand [PR120351] (*)
5768bc2... c: Fix crash in c-typeck.cc convert_arguments with indirect (*)
3913d95... c: Suppress -Wdeprecated-non-prototype warnings for builtin (*)
cb06e4a... tree-optimization/121323 - UBSAN error in ao_ref_init_from_ (*)
3ef3de7... tree-optimization/121320 - UBSAN error in ao_ref_init_from_ (*)
8fb94bb... bswap: Fix up ubsan detected UB in find_bswap_or_nop [PR121 (*)
ebfe7bc... c++/modules: Warn for optimize attributes instead of ICEing (*)
16e8d14... c++/modules: Merge PARM_DECL properties from function defin (*)
0d41077... Daily bump. (*)
fc03165... AVR: rtl-optimization/121340 - New mini-pass to undo superf (*)
87a2b9d... AVR: Set .type of jump table label. (*)
df63b4a... c++: constexpr, array, private ctor [PR120800] (*)
4cdf858... Ada: Fix miscompilation of GNAT tools with -march=znver3 (*)
80f7f22... [sanitizer_common] Fix build on ppc64+musl (#120036) (*)
b3da180... aarch64: Prevent streaming-compatible code from assembler r (*)
9e84a45... aarch64: testsuite: Fix do-assemble tests for SME (*)
1212354... c++: substituting fn parm redeclared with dep alias tmpl [P (*)
35be043... c++: fix ICE with [[deprecated]] [PR120756] (*)
295dd13... tree-optimization/121256 - re-instantiate check on SLP node (*)
c70696b... [RISC-V] Fix wrong CFA during stack probe (*)
4686007... change get_best_mode args int -> HOST_WIDE_INT [PR121264] (*)
1b42af2... Fix ICE in speculative devirtualization (*)
e442d6f... tree-optimization/121256 - properly support SLP in vectoriz (*)
5e9d395... tree-optimization/121130 - vectorizable_call cannot handle (*)
1869281... vect: Fix insufficient alignment requirement for speculativ (*)
94ca071... x86: Transform to "pushq $-1; popq reg" for -Oz (*)
82cc62b... Eliminate redundant vpextrq/vpinsrq when move TI to V4SI. (*)
6d0aa94... Daily bump. (*)
3d15aa4... [sanitizer_common] Remove reference to obsolete termio ioct (*)
d36df2a... Update cpplib sr.po (*)
722aa41... C: Flex array in union followed by a structure field is not (*)
12796e6... C: Flex array in the middle via type alias is not reported (*)
54cfe50... aarch64: Add tuning model for Olympus core. (*)
281a6a0... c++: Make __extension__ silence -Wlong-long pedwarns/warnin (*)
9a5a5e8... testsuite: Fix gcc.target/powerpc/vsx-builtin-7.c test [PR1 (*)
7b9838d... Daily bump. (*)
4e56845... cobol: Honor the "-static" command-line option. [PR119231] (*)
0879a2a... cobol: Tweak adjustments to location_t of GENERIC nodes for (*)
84296ba... cobol: Improved linemap and diagnostic handling; PIC valida (*)
f27c6d8... cobol: Eliminate cppcheck warnings in gcc/cobol .cc files. (*)
7dc3a37... cobol: Minor changes to genapi.cc to eliminate CPPCHECK war (*)
79c7ed9... cobol: Fix build on 32-bit Darwin [PR120621] (*)
d780100... cobol: Add PUSH and POP to CDF. (*)
4a3e130... cobol: Development round-up. [PR120765, PR119337, PR120794] (*)
2e50844... cobol: Respect error in cobol.install-common. (*)
8536d47... cobol: Repair printf format of size_t. (*)
1951807... cobol: Update test case for intrinsic function syntax. (*)
d6115f7... cobol: Revise diagnostic linemap management. (*)
3f8dfda... cobol: Normalize generating and using function_decls. (*)
9717324... cobol: Correct diagnostic strings for 32-bit builds. (*)
fd73532... libgcobol: Add license. (*)
efc75cb... cobol: Correct diagnostic strings to rectify bootstrap buil (*)
f3dc4a5... cobol: Some 1000 small changes in answer to cppcheck diagno (*)
8df603c... cobol: Eliminate unguarded clock_gettime dependencies. [PR1 (*)
f79a7d0... cobol: Variety of small changes in answer to cppcheck diagn (*)
cd1fd18... cobol: Diagnostic messages, Flex build, and some cppcheck r (*)
6c214d4... cobol: Guard clock_gettime(). [PR119975] (*)
ddf7357... cobol: Eliminate cppcheck warnings for libgcobol [PR119323] (*)
c48cce8... cobol: Honor HAVE_CLOCK_GETTIME and HAVE_GETTIMEOFDAY. [PR1 (*)
7305d78... cobol: Wrap the call to fprintf in a libgcobol routine. [PR (*)
907e343... cobol: Multiple PRs; formatting; exception processing. (*)
e7f1334... cobol: sqrt(0) is not an ec-argument error. [PR119885] (*)
d33eb83... Regenerate cobol/lang.opt.urls (*)
08e58db... cobol: Eliminate exception "blob"; streamline some code gen (*)
aa66c62... cobol: One additional edit to testsuite/cobol.dg/group1/che (*)
412994e... cobol: Don't display 0xFF HIGH-VALUE characters in testcase (*)
5ce4d3e... libgcobol: Allow for lack of LOG_PERROR (*)
d6da95b... cobol: Eliminate padding bytes from cbl_declarative_t. [PR1 (*)
5a1de4d... cobol: New testcases. (*)
704bf38... cobol: Auto-detect source format; some FldLiteralN; infer g (*)
7fdeb67... libgcobol: Heed --enable-libgcobol (*)
1066f31... cobol: Allow for undefined NAME_MAX [PR119217] (*)
43bf1b3... cobol: Initialize regmatch_t portably [PR119217] (*)
320f24a... cobol: Don't require GLOB_BRACE etc. [PR119217] (*)
b61e85f... libgcobol: Fix bootstrap for targets without program_invoca (*)
1513f3c... cobol: Rewrite exception handling. Partially refactor subs (*)
167f366... cobol: Fix up exception handling [PR119364] (*)
adffa53... cobol, v2: Fix up cobol cross-compilation from 32-bit arche (*)
d4ba7ea... cobol: New testcases. (*)
5915b1a... cobol: Repair some exception processing logic. (*)
636c0d5... libgcobol: Check for struct tm tm_zone (*)
50c9168... testsuite: Adjust s390x params for vector tests. (*)
c677121... Darwin: account for macOS 26 (*)
f67c851... c++, coroutines: Handle allocation fail returns [PR121219]. (*)
823d594... c++: add passing testcases [PR120243] (*)
b4da8ee... c++, coroutines: CWG2563 promise lifetime extension [PR1159 (*)
a169a47... c++, coroutines: Remove use of coroutine handle in the fram (*)
892892b... c++,coroutines: Handle await expressions in assume attribut (*)
f4ae768... c++, coroutines: Handle unevaluated contexts. (*)
38db03d... c++, coroutines: Avoid UNKNOWN_LOCATION synthesizing code [ (*)
a2328db... c++, coroutines: Improve diagnostics for awaiter/promise. (*)
a94894f... c++, coroutines: Handle builtin_constant_p [PR116775]. (*)
956b6c3... c++, coroutines: Ensure that the resumer is marked as can_t (*)
e25730c... c++: Fix template class lookup [PR120495, PR115605]. (*)
11cab98... c++, coroutines: Make analyze_fn_params into a class method (*)
81e04fd... c++, coroutines: Simplify initial_await_resume_called. (*)
f3fbacc... c++, coroutines: Some cleanups in build_actor. (*)
b9b3471... c++: Emit an error for attempted constexpr co_await [PR1189 (*)
ad8c618... c++: Add co_await, co_yield and co_return to dump_expr. (*)
20a4cf9... c++, coroutines: Make a check more specific [PR109283]. (*)
ae9ccc7... c++, coroutines: Clean up the ramp cleanups. (*)
df99f2d... c++, coroutines: Use decltype(auto) for the g_r_o. (*)
db4a02c... c++, coroutines: Address CWG2563 return value init [PR11991 (*)
4b2da16... c++, coroutines: Fix identification of coroutine ramps [PR1 (*)
491b8b2... c++, coroutines: Allow NVRO in more cases for ramp function (*)
868a11b... c++: Set the outer brace marker for missed cases. (*)
b1b8d8c... tree-sra: Avoid total SRA if there are incompat. aggregate (*)
4af2b71... calls: Allow musttail calls to noreturn [PR121159] (*)
6e51957... x86: Enable *mov<mode>_(and|or) only for -Oz (*)
44bb1a5... Daily bump. (*)
42c37c2... AVR: target/121277 - Don't load 0x800000 with const __flash (*)
e8463da... Fortran: Allow for iterator substitution in array construct (*)
0a624fe... LoongArch: Fix wrong code generated by TARGET_VECTORIZE_VEC (*)
7dba3eb... Daily bump. (*)
93eeb52... [RISC-V] Correct CFA notes for stack-clash protection [PR12 (*)
4f3b1f3... Daily bump. (*)
b26588f... gcse: Skip hardreg pre when the hardreg is never live [PR12 (*)
e34c0fe... aarch64: Fix fma steering when rename fails [PR120119] (*)
4cb9e69... Fortran: fix passing of character length of function to pro (*)
3ba8769... [PATCH] [modula2] Add return to remove build warning (*)
f9773b1... [PATCH] PR modula2/121164: Modula 2 build failure followup (*)
a4bdd2b... Daily bump. (*)
6f0c684... c++: constexpr uninitialized union [PR120577] (*)
2fb7db8... ada: Bug in Indefinite_Holders instance passed to formal pa (*)
9662803... ada: Fix regression of finalization primitive selection (*)
82a93f6... Daily bump. (*)
80a51da... c++: fix __is_invocable for std::reference_wrapper [PR12105 (*)
5a29c91... libstdc++: Add missing initializers for __maybe_present_t m (*)
4d0c173... tree-optimization/121202 - fix vector stmt placement (*)
efce571... c++/modules: Support re-streaming TU_LOCAL_ENTITYs [PR12041 (*)
5970feb... Daily bump. (*)
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