Messages by Thread
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sscounterenw extension.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sm/scsrind extensions.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Ssccptr extension.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Shlcofideleg extension.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update extension defination.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vdiv.vx combine
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Add svbare extension.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Leverage get_vector_binary_rtx_cost to avoid code dup [NFC]
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1 with GR2VR cost 0, 1 and 2
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0 with GR2VR cost 0, 2 and 15
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Add smcntrpmf extension.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use helper function to get FPR to VR move cost
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-riscv-ext-texi
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100]
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Implement full-featured iterator for riscv_subset_list [NFC]
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mode.c
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for avg_ceil vaadd implementation
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix line too long format issue for autovect.md [NFC]
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for avg_ceil
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add minimal support of double trap extension 1.0
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmul.vv combine case 1 with GR2VR cost 0, 1 and 2
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR cost
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for avg_floor vaadd implementation
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for avg_floor
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Avoid division by zero in check_builtin_call [PR120436].
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Leverage vaadd.vv for signed standard name avg_floor
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add andi+bclr synthesis
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vxor.vv combine case 1 with GR2VR cost 0, 1 and 2
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost 0, 2 and 15
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] shift+and+shift for logical and synthesis
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vor.vv combine case 1 with GR2VR cost 0, 1 and 2
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR cost
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support CPUs in -march.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix some dynamic LMUL costing.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add autovec mode param.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Clear both upper and lower bits using 3 shifts
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Default-initialize variable.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level.
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Clear high or low bits using shift pairs
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120368] Fix 32bit shift on rv64
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Improve (x << C1) + C2 split code
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vand.vv combine case 1 with GR2VR cost 0, 1 and 2
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vand.vv combine case 0 with GR2VR cost 0, 2 and 15
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Infrastructure of synthesizing logical AND with constant
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performanc
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the sa
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Avoid multiple assignments to output object
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC]
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 1
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 15
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed][RISC-V][PR target/120333] Remove bogus bext pattern
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Fix false positive from Wuninitialized
Jeff Law via Gcc-cvs
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[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix the warning of temporary object dangling references.
Jeff Law via Gcc-cvs