https://gcc.gnu.org/g:1477bbe4b5002b4a00057e6dd25fcbc01fae1406
commit r15-6013-g1477bbe4b5002b4a00057e6dd25fcbc01fae1406
Author: Eric Botcazou <ebotca...@adacore.com>
Date: Sat Dec 7 19:53:53 2024 +0100
SPARC: Add functional comments for VIS4B instructions
gcc/
* config/sparc/sparc.md (VIS4B instructions): Add comments.
Diff:
---
gcc/config/sparc/sparc.md | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 5fd18b3ca27c..159518d4b8fd 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -9466,10 +9466,14 @@
[(set_attr "type" "fp")
(set_attr "fptype" "double")])
-;; VIS4B instructions.
+;; VIS4B instructions (specified in the unpublished OSA 2017)
(define_mode_iterator DUMODE [V8QI V4HI V2SI])
+;; Unpack a DUMODE right-justified value from {8,4,2} consecutive bitfields of
(opnd 1):
+;; for 0 <= (opnd 2) <= 7 : V8QI value from 8 consecutive bitfields of (opnd
2) + 1 bits
+;; for 8 <= (opnd 2) <= 15: V4HI value from 4 consecutive bitfields of (opnd
2) + 1 bits
+;; for 16 <= (opnd 2) <= 31: V2SI value from 2 consecutive bitfields of (opnd
2) + 1 bits
(define_insn "dictunpack<DUMODE:vbits>"
[(set (match_operand:DUMODE 0 "register_operand" "=e")
(unspec:DUMODE [(match_operand:DF 1 "register_operand" "e")
@@ -9480,6 +9484,7 @@
[(set_attr "type" "fga")
(set_attr "subtype" "other")])
+;; Same as fpcmp but the {8,4,2}-bit result is shifted left by (opnd 3) *
{8,4,2}
(define_insn "fpcmp<fpcmpcond:code><FPCMP:vbits><P:mode>shl"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(fpcmpcond:FPCMP (match_operand:FPCMP 1 "register_operand"
"e")
@@ -9490,6 +9495,7 @@
"fpcmp<fpcmpcond:code><FPCMP:vbits>shl\t%1, %2, %3, %0"
[(set_attr "type" "viscmp")])
+;; Same as fpcmpu but the {8,4,2}-bit result is shifted left by (opnd 3) *
{8,4,2}
(define_insn "fpcmpu<fpcmpucond:signed_code><FPCMP:vbits><P:mode>shl"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(fpcmpucond:FPCMP (match_operand:FPCMP 1 "register_operand"
"e")
@@ -9500,6 +9506,9 @@
"fpcmpu<fpcmpucond:signed_code><FPCMP:vbits>shl\t%1, %2, %3, %0"
[(set_attr "type" "viscmp")])
+;; Dual Equal comparison: the unshifted result is the OR of two EQ comparisons
+;; of (opnd 1) with 1) the 32-bit highpart of (opnd 2) concatenated with itself
+;; and 2) the 32-bit lowpart of (opnd 2) concatenated with itself.
(define_insn "fpcmpde<FPCMP:vbits><P:mode>shl"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(match_operand:FPCMP 1 "register_operand" "e")
@@ -9510,6 +9519,10 @@
"fpcmpde<FPCMP:vbits>shl\t%1, %2, %3, %0"
[(set_attr "type" "viscmp")])
+;; Unsigned Range comparison: the unshifted result is True if (opnd 1) lies in
+;; partitioned unsigned range (LB,HB) with LB) the 32-bit highpart of (opnd 2)
+;; concatenated with itself and HB) the 32-bit lowpart of (opnd 2) concatenated
+;; with itself.
(define_insn "fpcmpur<FPCMP:vbits><P:mode>shl"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(match_operand:FPCMP 1 "register_operand" "e")
