https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118935
--- Comment #30 from huangpei at loongson dot cn <huangpei at loongson dot cn> --- On Tue, Sep 01, 2026 at 04:30:29AM +0000, xry111 at gcc dot gnu.org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118935 > > --- Comment #29 from Xi Ruoyao <xry111 at gcc dot gnu.org> --- > (In reply to Jerry DeLisle from comment #28) > > I have lost track here. It seems that the patch given in comment #16 fixes > > the issue but there is something wrong on the the 3A6000? > > I mean comment #25 indicated the issue was not reproducible *even without the > patch* on 3A6000 but I can reproduce it there (still without the patch). So > something in the discussions leading to the conclusion that the issue only > affects the "very weak order" implementations like 3A5000 does not add up. > > I'm not so concerning about this though, as data race is clearly an undefined > behavior so any difference can be simply explained as "just good/bad luck." Please check whether CPUCFG.3.LD_SEQ_SA[bit23] return 1 on your 3A6000, + if return 0, then 3A6000 is configured same as 3A5000 on SA-RAR-OoO (Same address Read After Read Out of Order) + if return 1, then 3A6000 is cache coherent without this issue. > > -- > You are receiving this mail because: > You are on the CC list for the bug. > You are the assignee for the bug.
