https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118935
--- Comment #25 from huangpei at loongson dot cn <huangpei at loongson dot cn> --- The English version is archived read-only, see Chinese version v1.1 Page 48 about dbar hint. (In reply to [email protected] from comment #24) > Am 14.08.26 um 11:59 schrieb huangpei at loongson dot cn: > > Base on Comment 6 and Comment 15, we can confirm that there is data race > > between > > find_file0 and set_internal_unit/new_unit, but Comment 15 show that **Only** > > under very weakly-order memory model with Same address Read after Read Out > > of > > Oder, SEGV can be triggered. As far as I know, Only Loong64 meet this memory > > modal. So I do not think this bug can be triggered on POWER64 or ARM64； > > Out of curiosity: Where is this documented? I cannot find this in > > https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1- > EN#overview-of-memory-consistency > > . 3A6000+, while compatible with 3A50000, has changed this behavior by new CPUCFG. So this is not a problem on newer cpu
