https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122665
Jeevitha <jeevitha at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Component|target |c
Keywords|wrong-code |
--- Comment #1 from Jeevitha <jeevitha at gcc dot gnu.org> ---
The pattern should look like below,
(define_insn "smul<mode>3_highpart"
[(set (match_operand:VIlong 0 "vsx_register_operand" "=wa")
(ashiftrt (mult:VIlong (match_operand:VIlong 1 "vsx_register_operand"
"v")
(match_operand:VIlong 2 "vsx_register_operand"
"v"))
(const_int 32)))]. // Todo: 32 for int and 64 for long
"TARGET_POWER10"
"vmulhs<wd> %0,%1,%2"
[(set_attr "type" "veccomplex")])
