https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122665
Bug ID: 122665
Summary: On rs6000 target define_insn pattern seems to be
incorrect for [su]mul_highpart
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: jeevitha at gcc dot gnu.org
Target Milestone: ---
Target: powerc64le-linux-gnu
Instruction definition for Vector Multiply High Signed Word:
vmulhsw VRT, VRA, VRB
do i = 0 to 3
src1 ← EXTS(VSR[VRA+32].word[i])
src2 ← EXTS(VSR[VRB+32].word[i])
VSR[VRT+32].word[i] ← CHOP32((src1 × src2) >> 32)
end
Our current RTL pattern looks like this:
(define_insn "smul<mode>3_highpart"
[(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
(mult:VIlong (ashiftrt
(match_operand:VIlong 1 "vsx_register_operand" "v")
(const_int 32))
(ashiftrt
(match_operand:VIlong 2 "vsx_register_operand" "v")
(const_int 32))))]
"TARGET_POWER10"
"vmulhs<wd> %0,%1,%2"
[(set_attr "type" "veccomplex")])
It seems that we are performing a right shift on both input operands before the
multiplication. But that’s not correct, right?
We actually need to perform the multiplication first, and then apply the right
shift after the multiplication to get the high part.
