[Bug target/120642] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:5705 with -O -mcpu=xt-c920 -mrvv-vector-bits=zvl

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120642

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <l...@gcc.gnu.org>:

https://gcc.gnu.org/g:f2e3886a30c771b104bc2714992e072b21a52e76

commit r16-2132-gf2e3886a30c771b104bc2714992e072b21a52e76
Author: Jeff Law <j...@ventanamicro.com>
Date:   Wed Jul 9 05:23:34 2025 -0600

    [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector

    AVL propagation currently assumes that it can propagate a constant AVL into
any
    vector insn and trips an assert if the insn fails to recognize after such a
    propagation.

    However, for xtheadvector that is not a correct assumption; xtheadvector
does
    not allow the vector length to be a constant integer (other than zero which
    allowed via x0).

    After consulting with Jin Ma (thanks!) we agree the right fix is to avoid
    creating the immediate AVL for xtheadvector.

    This has been tested in my tester, just waiting for the pre-commit tester
to
    spin it.

            PR target/120642
    gcc/
            * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Do not do
            constant AVL propagation for xtheadvector.

    gcc/testsuite/
            * gcc.target/riscv/rvv/xtheadvector/pr120642.c: New test.