[Bug target/120642] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:5705 with -O -mcpu=xt-c920 -mrvv-vector-bits=zvl

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120642

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW
           Assignee|rdapp.gcc at gmail dot com         |law at gcc dot gnu.org
                 CC|                            |majin at gcc dot gnu.org
   Last reconfirmed|                            |2025-07-07

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
So if I'm reading everything correctly, xtheadvector can't take a constant avl.
 We had this:

(set (reg:RVVM1DI 148)
    (unspec:RVVM1DI [
            (unspec:RVVMF64BI [
                    (const_vector:RVVMF64BI [
                            (const_int 1 [0x1]) repeated x2
                        ])
                    (reg:DI 149)
                    (const_int 2 [0x2]) repeated x2
                    (const_int 1 [0x1])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (unspec:RVVM1DI [
                    (reg:DI 0 zero)
                ] UNSPEC_VUNDEF)
            (subreg:RVVM1DI (reg:RVVM1SI 144 [ _6 ]) 0)
            (reg:DI 150)
        ] UNSPEC_VSLIDEDOWN))

And we wanted to replace (reg:DI 149) with (const_int 2) resulting in:

(set (reg:RVVM1DI 148)
    (unspec:RVVM1DI [
            (unspec:RVVMF64BI [
                    (const_vector:RVVMF64BI [
                            (const_int 1 [0x1]) repeated x2
                        ])
                    (const_int 2 [0x2]) repeated x3
                    (const_int 1 [0x1])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (unspec:RVVM1DI [
                    (reg:DI 0 zero)
                ] UNSPEC_VUNDEF)
            (subreg:RVVM1DI (reg:RVVM1SI 144 [ _6 ]) 0)
            (reg:DI 150)
        ] UNSPEC_VSLIDEDOWN))

Which doesn't match because the vector_length_operand predicate rejects nonzero
constants for XTHEADVECTOR.

I think the right fix here is to just guard the transformation in AVL
propagation like this:

```
diff --git a/gcc/config/riscv/riscv-avlprop.cc
b/gcc/config/riscv/riscv-avlprop.cc
index bb4aceb75064..3031c29ae63c 100644
--- a/gcc/config/riscv/riscv-avlprop.cc
+++ b/gcc/config/riscv/riscv-avlprop.cc
@@ -508,7 +508,7 @@ pass_avlprop::execute (function *fn)
       simplify_replace_vlmax_avl (rinsn, prop.second);
     }

-  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
+  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL && !TARGET_XTHEADVECTOR)
     {
       /* Simplify VLMAX AVL into immediate AVL.
         E.g. Simplify this following case:


```

But I've never really worked on theadvector.

Jin Ma -- any thoughts here?