[Bug target/120642] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:5705 with -O -mcpu=xt-c920 -mrvv-vector-bits=zvl

[majin at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120642

--- Comment #2 from Jin Ma <majin at gcc dot gnu.org> ---

> Which doesn't match because the vector_length_operand predicate rejects
> nonzero constants for XTHEADVECTOR.
> 
> I think the right fix here is to just guard the transformation in AVL
> propagation like this:
> 
> ```
> diff --git a/gcc/config/riscv/riscv-avlprop.cc
> b/gcc/config/riscv/riscv-avlprop.cc
> index bb4aceb75064..3031c29ae63c 100644
> --- a/gcc/config/riscv/riscv-avlprop.cc
> +++ b/gcc/config/riscv/riscv-avlprop.cc
> @@ -508,7 +508,7 @@ pass_avlprop::execute (function *fn)
>        simplify_replace_vlmax_avl (rinsn, prop.second);
>      }
>  
> -  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
> +  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL && !TARGET_XTHEADVECTOR)
>      {
>        /* Simplify VLMAX AVL into immediate AVL.
>          E.g. Simplify this following case:
> 
> 
> ```
> 
> But I've never really worked on theadvector.
> 
> Jin Ma -- any thoughts here?

Hi,Jeff

  Thank you for the feedback. Since XTheadVector lacks support for vsetivli,
your proposed method is the optimal workaround. By the way, if needed, I'd be
happy to submit a patch with test cases :)