https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119361
--- Comment #4 from Robin Dapp <rdapp at gcc dot gnu.org> --- (In reply to Edwin Lu from comment #3) > I'm not familiar enough with how the two modes interact with each other but > I guess my question is, why do we have so many conversions between the two > modes? What's the benefit of using VLA modes for VLS codegen and vice versa? > It seems rather counterintuitive to me to have these two modes blend > together regardless of compiling for vla or vls. Right, it's not that we use real VLA modes for VLS. Part of the issue is that we repurpose the names of our usual VLA modes (like RVVM1SI) to mean VLS modes. In our backend we have a number of instances of riscv_v_ext_vector_mode_p () which basically pattern matches the mode name. If we see a "VLA name" we go the VLA codegen route instead of the possibly simpler VLS one. At some point we also have VLS subregs of "VLA-name but actually VLS modes". This shouldn't be a problem because the middle end handles this correctly as long as we gave it the proper info but all in all it just doesn't really feel right. The difference between "VLA with minimum zvl" and "-mrvv-vector-bits = zvl == VLA with minimum zvl and maximum zvl" is that the separation in mode names is clear in the former but not the latter. In total it's not that bad but needs some work in the backend to get it right.
