https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119361
--- Comment #2 from Robin Dapp <rdapp at gcc dot gnu.org> --- I looked into this some more and it points to a general deficiency in how we handle the split between VLA and VLS modes. With ...bits=zvl the RVVM1SI etc modes. become VLS modes. In turn, this means that whenever we expand e.g. a vector(4) int we get an RVVM1SI mode back. But not all expanders (like vec_extract) are implemented for those modes but just for the "real" VLS modes like V4SI. As we "convert" back and forth between those modes and lack some expanders the resulting code is worse. I think a bit of an overhaul is necessary here for GCC 16. Right now I suppose for some cases you'll get better codegen without ...bits=zvl. There are also cases where zvl gets us better code, though :/
