[Bug rtl-optimization/119127] [15 Regression] ICE in decompose, at rtl.h:2312 during RTL pass: late_combine

[chenglulu at loongson dot cn via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119127

--- Comment #4 from chenglulu <chenglulu at loongson dot cn> ---
(In reply to Xi Ruoyao from comment #3)
> It happens at:
> 
> trying to combine definition of r94 in: 
>    15: r94:DI=r92:DI<<0x2&0xfffffffc
>       REG_DEAD r92:DI
> into:
>    17: r96:DI=sign_extend(r87:SI+r94:DI#0)
>       REG_DEAD r94:DI
>       REG_DEAD r87:SI
> 
> i.e.
> 
> bstrpick.d t0, a0, 31, 0
> slli.d     t0, t0, 2
> addi.w     t0, t0, a1
> 
> But we want just
> 
> alsl.w     t0, a0, a1, 2
> 
> It seems modifying SImode to DImode as comment 1 will defeat the
> optimization.  I guess we should sign extend mask in
> loongarch_reassoc_shift_bitwise to mode if it's not already sign-extended.

I disagree with your viewpoint.  Like the optimization below.
If the mask is sign-extended here, an error will occur.

(insn 17 13 28 2 (set (reg:DI 14 $r14 [96])
        (sign_extend:DI (plus:SI (subreg/s/u:SI (and:DI (ashift:DI (reg:DI 14
$r14 [96])
                            (const_int 2 [0x2]))
                        (const_int 4294967292 [0xfffffffc])) 0)
                (reg:SI 12 $r12 [orig:87 _3 ] [87])))) "pr119127.ii":11:39 266
{and_alsl_reversesi_extended}
     (nil)) 

split to :
(insn 32 13 33 2 (set (reg:DI 14 $r14 [96])
        (and:DI (reg:DI 14 $r14 [96])
            (const_int 1073741823 [0x3fffffff]))) "pr119127.ii":11:39 101
{*anddi3}
     (nil))
(insn 33 32 28 2 (set (reg:DI 14 $r14 [96])
        (sign_extend:DI (plus:SI (ashift:SI (reg:SI 14 $r14 [96])
                    (const_int 2 [0x2]))
                (reg:SI 12 $r12 [orig:87 _3 ] [87])))) "pr119127.ii":11:39 256
{*alslsi3_extend}
     (nil))