[Bug rtl-optimization/119127] [15 Regression] ICE in decompose, at rtl.h:2312 during RTL pass: late_combine

[chenglulu at loongson dot cn via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119127

--- Comment #1 from chenglulu <chenglulu at loongson dot cn> ---
This patch can fix the problem.
However, there are some parts that I haven't quite understood yet.

```
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index 90c475ef0c0..80b2feb3457 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -3174,7 +3174,7 @@ (define_insn_and_split "<optab>_alsl_reversesi_extended"
            (match_operand:SI 4 "register_operand" "r"))))]
   "TARGET_64BIT
    && loongarch_reassoc_shift_bitwise (<is_and>, operands[2], operands[3],
-                                      SImode)"
+                                      DImode)"
   "#"
   "&& reload_completed"
   [; r0 = r1 [&|^] r3 is emitted in PREPARATION-STATEMENTS because we
@@ -3187,7 +3187,7 @@ (define_insn_and_split "<optab>_alsl_reversesi_extended"
     operands[3] = loongarch_reassoc_shift_bitwise (<is_and>,
                                                   operands[2],
                                                   operands[3],
-                                                  SImode);
+                                                  DImode);

     if (ins_zero_bitmask_operand (operands[3], SImode))
       {

```