[Bug target/117955] [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117955

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
>From my reading of the V 1.0 spec, `vsetvli zero,zero,e64,mf4,ta,ma` should be
valid still.