[Bug target/113281] [14] RISC-V rv64gcv_zvl256b vector: Runtime mismatch with rv64gc

[juzhe.zhong at rivai dot ai via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281

--- Comment #4 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Confirm reduced case:

#include <assert.h>
unsigned char a;

int main() {
  short b = a = 0;
  for (; a != 19; a++)
    if (a)
      b = 32872 >> a;

  assert (b == 0);
}

with -fno-vect-cost-model -march=rv64gcv -O3:

https://godbolt.org/z/joGb3e9Eb

Also run failed assertion "b == 0" failed: file "bug.c", line 10, function:
main

I suspect ARM SVE has the same fail.

Hi, Andrew. Could you test this case on ARM to see whether ARM has same issue
as RISC-V for me ?