[Bug middle-end/112854] [14] RISCV ICE: expand: in store_integral_bit_field, at expmed.cc:1049 on rv32gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112854

--- Comment #3 from Robin Dapp <rdapp at gcc dot gnu.org> ---
The problem seems to be that we can overlay a 32-bit bitmask with an SImode
subreg and work with it.  For zvl1024b on rv32 we don't allow this causing the
ICE.

We might be able to work around it by providing a vec_init for mask modes so we
don't use the subreg code.  I wonder why the vec_duplicate expander we already
have is not sufficient, though. Need to see where things go wrong.