[Bug target/109092] [13 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1932 when building libgcc on riscv64

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <k...@gcc.gnu.org>:

https://gcc.gnu.org/g:02880e7803b19c357718abd2f0d567b4a761f318

commit r13-6733-g02880e7803b19c357718abd2f0d567b4a761f318
Author: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
Date:   Mon Mar 13 22:17:57 2023 +0800

    RISC-V: Use reg_or_subregno to check regno [PR109092]

    gcc/ChangeLog:

            PR target/109092
            * config/riscv/riscv.md: Fix subreg bug.