[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602

--- Comment #20 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Yea, I think so (3 shifts).  Two for masking, one to put the bits in the right
position.  Then we just have to figure out how to combine the initial shift
with the 3 for the masking and ultimately result with just two :-)