[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

[vineetg at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602

--- Comment #11 from Vineet Gupta <vineetg at rivosinc dot com> ---

This definitely seems worth pursuing:

For bitmanip, following four insn seq matches

  Trying 7, 8, 6 -> 9:
    7: r78:DI=0x4000000000

    8: r77:DI=r78:DI-0x40
      REG_EQUAL 0x3fffffffc0

    6: r76:DI=r79:DI<<0x6

    9: r75:DI=r76:DI&r77:DI

  Successfully matched this instruction:
  (set (reg:DI 75)
     (and:DI (ashift:DI (reg:DI 79)

For non-bitmanip, a similar 3 insn seq doesn't

  Trying 9, 6 -> 10:
    9: r77:DI=r79:DI-0x40
      REG_EQUAL 0x3fffffffc0

    6: r76:DI=r80:DI<<0x6

   10: r75:DI=r76:DI&r77:DI

  Failed to match this instruction:
  (set (reg:DI 75)
    (and:DI (plus:DI (reg:DI 79)
            (const_int -64 [0xffffffffffffffc0]))
        (ashift:DI (reg:DI 80)
            (const_int 6 [0x6]))))

If we re-ran last failing case with REQ_EQUAL note it would match.