https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602
--- Comment #23 from Vineet Gupta <vineetg at rivosinc dot com> ---
(In reply to Jeffrey A. Law from comment #20)
> Yea, I think so (3 shifts). Two for masking, one to put the bits in the
> right position. Then we just have to figure out how to combine the initial
> shift with the 3 for the masking and ultimately result with just two :-)
Does combine handle 3 split outputs ?
If I hack my define_split to only have 2, I can see it split + matching the 2
insn (final codegen is obviously bogus)
Trying 7, 8, 9 -> 10:
7: r78:DI=0x1
8: r79:DI=r78:DI<<0x26
REG_DEAD r78:DI
REG_EQUAL 0x4000000000
9: r77:DI=r79:DI-0x40
REG_DEAD r79:DI
REG_EQUAL 0x3fffffffc0
10: r75:DI=r76:DI&r77:DI
REG_DEAD r77:DI
REG_DEAD r76:DI
Failed to match this instruction:
(set (reg:DI 75)
(and:DI (reg:DI 76)
(const_int 274877906880 [0x3fffffffc0])))
Splitting with gen_split_37 (riscv.md:2089)
Successfully matched this instruction:
(set (reg:DI 77)
(lshiftrt:DI (reg:DI 76) <-------
(const_int 6 [0x6])))
Successfully matched this instruction:
(set (reg:DI 75)
(ashift:DI (reg:DI 77) <-------
(const_int 32 [0x20])))
