https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104049
--- Comment #16 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Tamar Christina <tnfch...@gcc.gnu.org>: https://gcc.gnu.org/g:024edf08959e9c1d5022901e6c4e5cbaa5b6c8d5 commit r12-8045-g024edf08959e9c1d5022901e6c4e5cbaa5b6c8d5 Author: Tamar Christina <tamar.christ...@arm.com> Date: Thu Apr 7 08:27:53 2022 +0100 AArch64: Fix left fold sum reduction RTL patterns [PR104049] As the discussion in the PR pointed out the RTL we have for the REDUC_PLUS patterns are wrong. The UNSPECs are modelled as returning a vector and then in an expand pattern we emit a vec_select of the 0th element to get the scalar. This is incorrect as the instruction itself already only returns a single scalar and by declaring it returns a vector it allows combine to push in a subreg into the pattern, which causes reload to make duplicate moves. This patch corrects this by removing the weird indirection and making the RTL pattern model the correct semantics of the instruction immediately. gcc/ChangeLog: PR target/104049 * config/aarch64/aarch64-simd.md (aarch64_reduc_plus_internal<mode>): Fix RTL and rename to... (reduc_plus_scal_<mode>): ... This. (reduc_plus_scal_v4sf): Moved. (aarch64_reduc_plus_internalv2si): Fix RTL and rename to... (reduc_plus_scal_v2si): ... This. gcc/testsuite/ChangeLog: PR target/104049 * gcc.target/aarch64/vadd_reduc-1.c: New test. * gcc.target/aarch64/vadd_reduc-2.c: New test.
