https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104049
--- Comment #14 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> --- FWIW, I agree with Vlad that this isn't an RA problem. Some aarch64 instruction patterns are accepting operands that will inevitably require a reload. In principle we could tighten the predicates so that we reject these kinds of subreg for operands that only allow GPRs (not FPRs). But that just shifts the problem elsewhere. Some of these patterns do support w->w, so the net effect would be to lose out on some useful combinations without fixing the actual problem. I guess we should use an STV-like pass to do vector vs. scalar instruction selection, with that pass being the one that forces separate moves when (subreg:xI (reg:VnxI R) 0) occurs in a “scalar” instruction. Would be good to make it relatively target-independent though. So IMO we should fix RTL representation problem that Andrew pointed out in comment 7 as the P1 fix, then accept the other cases as a P2 regression caused by bigger improvements elsewhere.
