https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96744
--- Comment #7 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Uroš Bizjak from comment #5)
> (In reply to Hongtao.liu from comment #2)
>
> > Need to add define_insn for movp2qi/movp2hi?
>
> Yes, this is needed to cover some corner cases. Please see attachment 49114
> [details].
>
> However, the patch assumes that avx512vp2intersect implies mavx512dq,
Let me check this part.
> otherwise there is no direct QImode move from mask register to memory
> available.
and QImode masks would be indirectly stored through Q_REG.
cut from ix86_secondary_reload
---
/* QImode spills from non-QI registers require
intermediate register on 32bit targets. */
if (mode == QImode
&& ((!TARGET_64BIT && !in_p
&& INTEGER_CLASS_P (rclass)
&& MAYBE_NON_Q_CLASS_P (rclass))
|| (!TARGET_AVX512DQ
&& MAYBE_MASK_CLASS_P (rclass))))
{
int regno = true_regnum (x);
/* Return Q_REGS if the operand is in memory. */
if (regno == -1)
return Q_REGS;
return NO_REGS;
---
if we disable direct movement between gpr and masks in
inline_secondary_memory_needed, how should pass_reload spill QImode mask to
memeory, would it be functionality issue?
That's why i prefer changing cost model to disable spill to mask in general
target, as your patch "Retune mask <-> general moves cost" shows: attachment
49107
