https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96744
--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #5)
> However, the patch assumes that avx512vp2intersect implies mavx512dq,
> otherwise there is no direct QImode move from mask register to memory
> available.
This is the testcase:
--cut here--
typedef unsigned char __mmask8;
typedef unsigned short __mmask16;
typedef long long __m512i __attribute__ ((__vector_size__ (64),
__may_alias__));
typedef int __v16si __attribute__ ((__vector_size__ (64)));
typedef long long __v8di __attribute__ ((__vector_size__ (64)));
void
_mm512_2intersect_epi64 (__m512i __A, __m512i __B, __mmask8 *__U,
__mmask8 *__M)
{
__builtin_ia32_2intersectq512 (__U, __M, (__v8di) __A, (__v8di) __B);
}
--cut here--
cc1 -O2 -march=k8 -mavx512vp2intersect -mavx512bw pr96744.c
pr96744.c:13:1: error: insn does not satisfy its constraints:
13 | }
| ^
(insn 24 9 25 2 (set (mem/c:QI (plus:DI (reg/f:DI 7 sp)
(const_int -2 [0xfffffffffffffffe])) [1 %sfp+-2 S1 A16])
(reg:QI 68 k0 [86])) "pr96744.c":12:3 77 {*movqi_internal}
(expr_list:REG_DEAD (reg:QI 68 k0 [86])
(nil)))
during RTL pass: cprop_hardreg
compiles OK when -mavx512dq is added.
