http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50088
--- Comment #17 from Richard Guenther <rguenth at gcc dot gnu.org> 2011-08-17
14:42:11 UTC ---
(In reply to comment #16)
> The testcase has ...
>
> int n8 = (arr[7] * 9 + 8) & 15;
>
> for (i = 0; i < len; i+=8)
> {
> n1 = (n1 + 1) & 15;
>
> s += arr[i] << n1;
>
> The shift count is 32bit, which causes 32bit spill. Since shift/rotate
> instructions only take 8bit register (CL) as shift count, we load 8bit
> into CL. How do we solve this?
Well, always load from the spill slot with the mode the reg was spilled
if the arch says that is prefered.
