http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50088
--- Comment #15 from Ilya Enkovich <enkovich.gnu at gmail dot com> 2011-08-17 14:16:27 UTC --- (In reply to comment #14) > > I think this problem is unique to x86 since some instructions have > different sizes in register operands. In this example, shift count > is CL regardless the source operand size. I am not sure how much RA > can help here. By making register operands in shift instructions to > have the same size (32bit or less), it may work for most cases. > We have a problem due to different sizes of spill and load generated by IRA for the same var. I'm not sure that by patching shift instructions we cover all cases when IRA may do that.
