------- Comment #4 from krebbel at gcc dot gnu dot org 2005-12-07 11:26 ------- (In reply to comment #3) > BTW, is the s390 hw really masking the shift count with 63 for all insns, > or just the DImode shifts and with 31 for SImode shifts? On S/390 all shift count operands are masked with 63. SImode as well as DImode shifts.
There are actually two target macros trying to address this issue: SHIFT_COUNT_TRUNCATED and TARGET_SHIFT_TRUNCATION_MASK. If you set SHIFT_COUNT_TRUNCATED to 1 the default used as truncation mask will be GET_MODE_BITSIZE (mode) - 1 which is what you proposed. In the S/390 case we need a truncation mask of always 63 what I tried to introduce with this patch: http://gcc.gnu.org/ml/gcc-patches/2005-03/msg00207.html But this unfortunately doesn't help to get rid of pointless ANDs because TARGET_SHIFT_TRUNCATION_MASK is defined to be valid only for SHIFTs coming from named patterns. That makes it unusable for combine because it can't determine whether a SHIFT was generated due to a middle end optimization or due to a named pattern. For more information see (especially the mail from Richard Sandiford): http://gcc.gnu.org/ml/gcc/2005-04/msg01066.html If sometimes in the future all middle end optimizations touching SHIFTs will be aware of the target macro we can remove the duplicated shift pattern I'm about to introduce in the S/390 back end. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=25268
