Hi Biju,
Thanks for your patch.
On Sat, Jul 04, 2026 at 10:34:18AM +0100, Biju wrote:
> From: Biju Das <[email protected]>
>
> Add Display Unit support for the Renesas RZ/G3L SoC (R9A08G046). It is
> similar to the one found on RZ/G2L, but has LVDS support.
>
> Signed-off-by: Biju Das <[email protected]>
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 22 ++++++++++++++++++-
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 4 ++++
> .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 4 ++++
> .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.h | 1 +
> 4 files changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> index 3d13f61d3c97..a8d841421a0b 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> @@ -55,6 +55,24 @@ static const struct rzg2l_du_device_info
> rzg2l_du_r9a07g044_info = {
> .mode_clock_max = 83500,
> };
>
> +static const struct rzg2l_du_device_info rzg2l_du_r9a08g046_info = {
> + .channels_mask = BIT(0),
> + .routes = {
> + [RZG2L_DU_OUTPUT_DSI0] = {
> + .possible_outputs = BIT(0),
> + .port = 0,
> + },
> + [RZG2L_DU_OUTPUT_DPAD0] = {
> + .possible_outputs = BIT(0),
> + .port = 1,
> + },
> + [RZG2L_DU_OUTPUT_LVDS0] = {
> + .possible_outputs = BIT(0),
> + .port = 2,
> + },
> + },
> +};
> +
> static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {
> .channels_mask = BIT(0),
> .routes = {
> @@ -81,6 +99,7 @@ static const struct rzg2l_du_device_info
> rzg2l_du_r9a09g077_info = {
> static const struct of_device_id rzg2l_du_of_table[] = {
> { .compatible = "renesas,r9a07g043u-du", .data =
> &rzg2l_du_r9a07g043u_info },
> { .compatible = "renesas,r9a07g044-du", .data =
> &rzg2l_du_r9a07g044_info },
> + { .compatible = "renesas,r9a08g046-du", .data =
> &rzg2l_du_r9a08g046_info },
> { .compatible = "renesas,r9a09g057-du", .data =
> &rzg2l_du_r9a09g057_info },
> { .compatible = "renesas,r9a09g077-du", .data =
> &rzg2l_du_r9a09g077_info },
> { /* sentinel */ }
> @@ -92,7 +111,8 @@ const char *rzg2l_du_output_name(enum rzg2l_du_output
> output)
> {
> static const char * const names[] = {
> [RZG2L_DU_OUTPUT_DSI0] = "DSI0",
> - [RZG2L_DU_OUTPUT_DPAD0] = "DPAD0"
> + [RZG2L_DU_OUTPUT_DPAD0] = "DPAD0",
> + [RZG2L_DU_OUTPUT_LVDS0] = "LVDS0"
> };
>
> if (output >= ARRAY_SIZE(names))
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> index baf076d69cda..0b86c5a01210 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> @@ -21,10 +21,12 @@ struct device;
> struct drm_property;
>
> #define RZG2L_DU_FEATURE_DPIO_OE BIT(0) /* Has DPIO output enable
> control */
> +#define RZG2L_DU_FEATURE_SMUX2_DSI_CLK BIT(1) /* Per output mux */
This is not needed, we decide to move setting clock duty cycle handling into
encoder driver.
>
> enum rzg2l_du_output {
> RZG2L_DU_OUTPUT_DSI0,
> RZG2L_DU_OUTPUT_DPAD0,
> + RZG2L_DU_OUTPUT_LVDS0,
> RZG2L_DU_OUTPUT_MAX,
> };
>
> @@ -61,6 +63,7 @@ struct rzg2l_du_device_info {
> #define RZG2L_DU_MAX_CRTCS 1
> #define RZG2L_DU_MAX_VSPS 1
> #define RZG2L_DU_MAX_DSI 1
> +#define RZG2L_DU_MAX_LVDS 1
This is not used, please remove.
>
> struct rzg2l_du_device {
> struct device *dev;
> @@ -74,6 +77,7 @@ struct rzg2l_du_device {
> unsigned int num_crtcs;
>
> struct rzg2l_du_vsp vsps[RZG2L_DU_MAX_VSPS];
> + struct drm_bridge *lvds[RZG2L_DU_MAX_LVDS];
Same here.
> };
>
> static inline struct rzg2l_du_device *to_rzg2l_du_device(struct drm_device
> *dev)
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> index f50d166b764f..7315d437c2ea 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> @@ -105,6 +105,9 @@ int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu,
> return -EPROBE_DEFER;
> }
>
> + if (output == RZG2L_DU_OUTPUT_LVDS0)
> + rcdu->lvds[output - RZG2L_DU_OUTPUT_LVDS0] = bridge;
> +
Same here.
> dev_dbg(rcdu->dev, "initializing encoder %pOF for output %s\n",
> enc_node, rzg2l_du_output_name(output));
>
> @@ -115,6 +118,7 @@ int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu,
> return PTR_ERR(renc);
>
> renc->output = output;
> + renc->rcdu = rcdu;
Same.
> drm_encoder_helper_add(&renc->base, &rzg2l_du_encoder_helper_funcs);
>
> /* Attach the bridge to the encoder. */
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h
> b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h
> index 3e430c1f6132..8b048ca508be 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h
> @@ -17,6 +17,7 @@ struct rzg2l_du_device;
>
> struct rzg2l_du_encoder {
> struct drm_encoder base;
> + struct rzg2l_du_device *rcdu;
Same.
Thanks.
Kind Regards,
Tommaso
> enum rzg2l_du_output output;
> };
>
> --
> 2.43.0
>
