From: Biju Das <[email protected]> The DU block on the RZ/G3L SoC is identical to the one found on the RZ/G2L SoC. However, it supports the DSI, DPI, and LVDS interfaces, while the RZ/G2L supports only the DSI and DPI interfaces.
Due to this difference, a SoC-specific compatible string, 'renesas,r9a08g046-du', is added for the RZ/G3L SoC. Signed-off-by: Biju Das <[email protected]> --- .../bindings/display/renesas,rzg2l-du.yaml | 27 +++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 7c84a9ecc7a7..65368649fe77 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -20,6 +20,7 @@ properties: - enum: - renesas,r9a07g043u-du # RZ/G2UL - renesas,r9a07g044-du # RZ/G2{L,LC} + - renesas,r9a08g046-du # RZ/G3L - renesas,r9a09g057-du # RZ/V2H(P) - renesas,r9a09g077-du # RZ/T2H - items: @@ -65,7 +66,7 @@ properties: model-dependent. Each port shall have a single endpoint. patternProperties: - "^port@[0-1]$": + "^port@[0-2]$": $ref: /schemas/graph.yaml#/properties/port unevaluatedProperties: false @@ -88,7 +89,6 @@ required: - clocks - clock-names - power-domains - - ports - renesas,vsps additionalProperties: false @@ -108,6 +108,7 @@ allOf: port@0: description: DPI port@1: false + port@2: false required: - port@0 @@ -124,10 +125,31 @@ allOf: description: DSI port@1: description: DPI + port@2: false required: - port@0 - port@1 + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-du + then: + properties: + port: + properties: + endpoint@0: + description: DSI + endpoint@1: + description: DPI + endpoint@2: + description: LVDS + + required: + - port@0 + - port@1 + - port@2 - if: properties: compatible: @@ -140,6 +162,7 @@ allOf: port@0: description: DSI port@1: false + port@2: false required: - port@0 -- 2.43.0
