Hi Krzysztof Kozlowski, Thanks for the feedback.
> -----Original Message----- > From: Krzysztof Kozlowski <[email protected]> > Sent: 08 July 2026 09:30 > Subject: Re: [PATCH 01/16] dt-bindings: display: bridge: renesas,dsi: > Document RZ/G3L > > On Sat, Jul 04, 2026 at 10:34:11AM +0100, Biju wrote: > > From: Biju Das <[email protected]> > > > > The RZ/G3L DSI IP is similar to the RZ/G2L but has different global > > PHY timings and also the PLLCLK is ungateble clock. Add the compatible > > string "renesas,r9a08g046-mipi-dsi" to handle these difference for the > > Renesas RZ/G3L SoC. The power to DSI region is controlled by SYSC block. > > Document renesas,sysc-pwrrdy property to handle the power control. > > > > Signed-off-by: Biju Das <[email protected]> > > --- > > .../bindings/display/bridge/renesas,dsi.yaml | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > index c20625b8425e..b114ac3b111a 100644 > > --- > > a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam > > +++ l > > @@ -28,6 +28,7 @@ properties: > > - const: renesas,r9a09g057-mipi-dsi > > > > - enum: > > + - renesas,r9a08g046-mipi-dsi # RZ/G3L > > - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) > > > > reg: > > @@ -108,6 +109,20 @@ properties: > > power-domains: > > maxItems: 1 > > > > + renesas,sysc-pwrrdy: > > + description: > > + The system controller PWRRDY indicates to the DSI region, if the > > power > > + supply is ready. PWRRDY needs to be set during power-on before > > applying > > + any other settings. It also needs to be set before powering off the > > DSI. > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > This feels a lot like a power domain. Please elaborate what is PWRRDY and why > power-on/off and power > status within SoC (important!) is not encoded as power domain. We already tried modelling signal as power domain in RZ/G3S and finally Ulf agreed that it cannot be power-domain[1] " SYSC signal seems best to be modelled as a reset. Although, it looks like the USB PM domain provider should rather be the consumer of that reset, instead of having the reset being consumed by the consumers of the USB PM domain." Then Phillip proposed power sequencing driver[2] and finally he and Rob ok for the solution [3] [1] https://lore.kernel.org/all/CAPDyKFpLnREr4C=wz7o8lb-czbqa4nr2vtuydzhz26rcb1m...@mail.gmail.com/ [2] https://lore.kernel.org/all/[email protected]/#t [3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml?h=next-20260707&id=20eee0f69c9034a0f613528f829dcaca192740d5 Cheers, Biju
