On 7/6/26 11:56 PM, Akhil P Oommen wrote:
On 7/6/2026 4:37 PM, Anna Maniscalco wrote:
On 7/6/26 10:44 AM, Konrad Dybcio wrote:
On 7/5/26 9:13 PM, Anna Maniscalco wrote:
Program all the register needed to start up LPAC and send initialization
sequence.
Additionally, now that the LPAC ring is live, make the code aware of it.
Signed-off-by: Anna Maniscalco <[email protected]>
---
I believe some/all of these writes need to be guarded by if (has_lpac),
as many GPUs lack these registers and there may be side effects on
others
That's correct yeah. I'm not sure what has_lpac should be though.
Something we add to catalog? Or checking if it is a gen that has LPAC?
We can introduce a new QUIRK (ADRENO_QUIRK_LPAC?).
[...]
a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
- sizeof(u32) * gpu->nr_rings,
+ sizeof(u32) * (gpu->nr_rings + !!gpu-
lpac_rb),
Should we rename nr_rings to something like nr_XXX_rings
where XXX is some uarch-generic (i.e. not SQE because we also
support pre-a6xx) name for the main number cruncher?
Qualcom calls it GC so nr_gc_rings perhaps?
How about nr_gfx_rings as those rings can handle graphics workload?
That could be more intuitive yeah
-Akhil.
Konrad
Best regards,
Best regards,
--
Anna Maniscalco <[email protected]>
