[PATCH RFC 12/13] drm/msm: set ctxbank and asid based on ring

[Anna Maniscalco]

qcom-arm-smmu always maps asid and ctxbank 1:1 and lpac is always 1

Signed-off-by: Anna Maniscalco <anna.maniscalco2...@gmail.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 4417a9d04d7c..a8a061652ec2 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -247,7 +247,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
        struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
        phys_addr_t ttbr;
        bool is_lpac = ring == a6xx_gpu->base.base.lpac_rb;
-       u32 asid;
+       u32 asid, ctxbank;
        u64 memptr = rbmemptr(ring, ttbr0);
 
        if (ctx->seqno == ring->cur_ctx_seqno)
@@ -256,6 +256,9 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
        if (msm_iommu_pagetable_params(to_msm_vm(vm)->mmu, &ttbr, &asid))
                return;
 
+       /* qcom-arm-smmu always maps asid and ctxbank 1:1 */
+       ctxbank = asid = is_lpac;
+
        if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) {
                /* Wait for previous submit to complete before continuing: */
                OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4);
@@ -313,7 +316,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
                CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
                CP_SMMU_TABLE_UPDATE_1_ASID(asid));
        OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
-       OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
+       OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(ctxbank));
 
        /*
         * Write the new TTBR0 to the memstore. This is good for debugging.

-- 
2.54.0