> Subject: [v7 12/15] drm/i915/xelpd: Program Plane Post CSC Registers This needs to be i915/color:
> > Extract the LUT and program plane post csc registers. > > v2: Add DSB support > v3: Add support for single segment 1D LUT > v4: > - s/drm_color_lut_32/drm_color_lut32 (Simon) > - Move declaration to beginning of the function (Suraj) > - Remove multisegmented code, add it later > - Remove dead code for SDR planes, add it later > v5: > - Fix iterator issues > > Signed-off-by: Uma Shankar <[email protected]> > Signed-off-by: Chaitanya Kumar Borah <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_color.c | 59 ++++++++++++++++++++++ > 1 file changed, 59 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index 2a114d2964fa..86d1fbc906bf 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -3996,11 +3996,70 @@ xelpd_program_plane_pre_csc_lut(struct > intel_dsb *dsb, > } > } > > +static void > +xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, > + const struct intel_plane_state *plane_state) { > + struct intel_display *display = to_intel_display(plane_state); > + const struct drm_plane_state *state = &plane_state->uapi; > + enum pipe pipe = to_intel_plane(state->plane)->pipe; > + enum plane_id plane = to_intel_plane(state->plane)->id; > + const struct drm_color_lut32 *post_csc_lut = plane_state- > >hw.gamma_lut->data; > + u32 i, j, lut_size, lut_val; j is un-uninitialized here and it remains un-initialized even when first used can cause unforeseen errors Regards, Suraj Kandpal > + > + if (icl_is_hdr_plane(display, plane)) { > + intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), > + PLANE_PAL_PREC_AUTO_INCREMENT); > + /* TODO: Add macro */ > + intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), > + PLANE_PAL_PREC_AUTO_INCREMENT); > + if (post_csc_lut) { > + lut_size = 32; > + for (i = 0; i < lut_size; i++) { > + lut_val = > drm_color_lut32_extract(post_csc_lut[j++].green, 24); > + > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), > + lut_val); > + } > + > + /* Segment 2 */ > + do { > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), > + (1 << 24)); > + } while (++j < 34); > + } else { > + /*TODO: Add for segment 0 */ > + lut_size = 32; > + for (i = 0; i < lut_size; i++) { > + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); > + > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); > + } > + > + do { > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), > + 1 << 24); > + } while (i++ < 34); > + } > + > + intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); > + intel_de_write_dsb(display, dsb, > + > PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0); > + } > +} > + > static void > xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state > *plane_state) { > if (plane_state->hw.degamma_lut) > xelpd_program_plane_pre_csc_lut(dsb, plane_state); > + > + if (plane_state->hw.gamma_lut) > + xelpd_program_plane_post_csc_lut(dsb, plane_state); > } > > static const struct intel_color_funcs chv_color_funcs = { > -- > 2.50.1
