Hi Chris,
for consitency with other commits on this file, change your patch title:
drm: renesas: rz-du: Set DSI divider based on...
to
drm: renesas: rz-du: mipi_dsi: Set DSI divider based on...
On Wed, 5 Nov 2025 17:25:30 -0500
Chris Brandt <[email protected]> wrote:
> Before the MIPI DSI clock source can be configured, the target divide
> ratio needs to be known.
>
> Signed-off-by: Chris Brandt <[email protected]>
> Reviewed-by: Biju Das <[email protected]>
> Tested-by: Biju Das <[email protected]>
>
> ---
> v1->v2:
> - Add spaces around '/' in comments
> - Add target argument in new API
>
> v2->v3:
> - Add missing period in comment (Hugo)
> - Changed '1' to 'PLL5_TARGET_DSI' (Hugo)
> - Added Reviewed-by and Tested-by (Biju)
>
> v3->v4:
> - Fixed up the comments
> - Fixed the match for the divider to set (was missing a * 2)
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> index 3b52dfc0ea1e..301550f0ea9f 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -7,6 +7,7 @@
>
> #include <linux/bitfield.h>
> #include <linux/clk.h>
> +#include <linux/clk/renesas.h>
> #include <linux/delay.h>
> #include <linux/dma-mapping.h>
> #include <linux/io.h>
> @@ -732,6 +733,23 @@ static int rzg2l_mipi_dsi_host_attach(struct
> mipi_dsi_host *host,
>
By using an intermediate bpp variable, you can avoid a useless
second call to mipi_dsi_pixel_format_to_bpp():
unsigned int bpp;
...
bpp = mipi_dsi_pixel_format_to_bpp(device->format);
switch (bpp) {
case 24:
...
This also nicely matches your use of bpp in your comments/equations below:
> drm_bridge_add(&dsi->bridge);
>
> + /*
> + * Report the required division ratio setting for the MIPI clock
> dividers.
> + *
> + * VCO-->[POSTDIV1,2]--FOUTPOSTDIV-->| |-->[1/(DSI DIV A * B)]-->
> MIPI_DSI_VCLK
> + * | |-->|
> + * |-->[1/2]---FOUT1PH0-->| |-->[1/16]--------------->
> hsclk (MIPI-PHY)
> + *
> + * vclk * bpp = hsclk * 8 * num_lanes
> + *
> + * vclk * DSI_AB_divider = hsclk * 16
> + *
> + * which simplifies to...
> + * DSI_AB_divider = bpp * 2 / num_lanes
> + */
> + rzg2l_cpg_dsi_div_set_divider(mipi_dsi_pixel_format_to_bpp(dsi->format)
> * 2 / dsi->lanes,
> + PLL5_TARGET_DSI);
rzg2l_cpg_dsi_div_set_divider(bpp * 2 / dsi->lanes, PLL5_TARGET_DSI);
> +
> return 0;
> }
>
> --
> 2.50.1
>
>
--
Hugo Villeneuve
