Hi Chris, On Tue, 11 Nov 2025 19:39:25 +0000 Chris Brandt <[email protected]> wrote:
> Hi Hugo, > > On Tue, Nov 11, 2025 1:23 PM, Hugo Villeneuve wrote: > > I still don't know on which tree you based your patchset, just to be sure > > that I am not missing anything. > > > > Should it work on 6.17.7 stable tree or torvalds/master tree? > > I am using > https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git > > I have been testing with v6-18-rc2 (I have not pulled in the latest yet) > > Chris You still haven't provided the base-commit. There is a ton of branches in renesas-devel.git, so it is not easy to determine the branch/commit you used for your patchset. By providing base-commit, you will save everyone a lot of trouble. I tried to apply your patches on branch renesas-geert/master, using base-commit: 211ddde0823f I am using 4 lanes and a 24-bit panel, and a clock of 59MHz. Here is the relevant logs (I added some custom debug messages): [ 1.508000] rzg2l_cpg_dsi_div_set_divider(): dsi->lanes = 0 [ 1.508183] rzg2l_cpg_dsi_div_set_divider(): divider = 0 [ 1.513538] rzg2l_cpg_dsi_div_set_divider(): target = 1 ... [ 1.641377] [drm] cmdline forces connector DSI-1 panel_orientation to 3 [ 1.649264] [drm] Initialized rzg2l-du 1.0.0 for 10890000.display on minor 1 [ 1.656353] rzg2l-du 10890000.display: [drm] Device 10890000.display probed [ 1.680646] rzg2l-du 10890000.display: [drm] fb0: rzg2l-dudrmfb frame buffer device [ 1.688840] rzg2l-cpg 11010000.clock-controller: rzg2l_cpg_get_foutpostdiv_rate(): rate = 59000000 [ 1.701034] rzg2l-cpg 11010000.clock-controller: rzg2l_cpg_get_foutpostdiv_rate(): dsi_div_ab_desired = 0 [ 1.701042] rzg2l-cpg 11010000.clock-controller: rzg2l_cpg_get_foutpostdiv_rate(): hsclk = 0 [ 1.714490] rzg2l-cpg 11010000.clock-controller: hsclk out of range [ 1.714501] rzg2l-cpg 11010000.clock-controller: rzg2l_cpg_get_foutpostdiv_rate(): rate = 59000000 [ 1.729171] rzg2l-cpg 11010000.clock-controller: rzg2l_cpg_get_foutpostdiv_rate(): dsi_div_ab_desired = 0 [ 1.729178] rzg2l-cpg 11010000.clock-controller: rzg2l_cpg_get_foutpostdiv_rate(): hsclk = 0 [ 1.729184] rzg2l-cpg 11010000.clock-controller: hsclk out of range [ 1.729190] rzg2l-cpg 11010000.clock-controller: rzg2l_cpg_get_foutpostdiv_rate(): rate = 59000000 [ 1.729196] rzg2l-cpg 11010000.clock-controller: rzg2l_cpg_get_foutpostdiv_rate(): dsi_div_ab_desired = 0 [ 1.729201] rzg2l-cpg 11010000.clock-controller: rzg2l_cpg_get_foutpostdiv_rate(): hsclk = 0 ... The problem seems to be that dsi_div_ab_desired is not properly initialized, because the number of lanes is uninitialized (0) at this time, and therefore rzg2l_cpg_dsi_div_set_divider() gets called with its first parameter as zero. Like I said, it also happens on 6.17.7 stable tree. If I remove your patches, everything is fine. Hugo.
