Hi Chris,
On Wed, 5 Nov 2025 17:25:28 -0500
Chris Brandt <[email protected]> wrote:
> When the initial drivers were submitted, some of the timing was hard coded and
> did not allow for any MIPI-DSI panel to be attached.
> In general, panels or bridges can only be supported if MIPI-DSI lanes were 4.
> If the number of lanes were 3,2,1, the math no longer works out.
>
> A new API was created for the clock driver because the behaivior of the clock
> driver depends on DPI vs MIPI, the bpp, and the number of MIPI lanes.
>
>
> Testing:
> * RZ/G2L SMARC (MIPI-DSI to HDMI bridge, lanes = 4)
> * RZ/G2L-SBC (MIPI-DSI to LCD panel, lanes = 2)
> * RZ/G2UL SMARC (DPI to HDMI bridge)
> * Multiple monitors, multiple resolutions
>
>
>
> Chris Brandt (2):
> clk: renesas: rzg2l: Remove DSI clock rate restrictions
> drm: renesas: rz-du: Set DSI divider based on target MIPI device
>
> drivers/clk/renesas/rzg2l-cpg.c | 147 ++++++++++++++++--
> .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 18 +++
> include/linux/clk/renesas.h | 12 ++
> 3 files changed, 164 insertions(+), 13 deletions(-)
>
> --
> 2.50.1
Your patchset is missing the base-commit tag like in this example:
base-commit: 4e68ae36422e85ec1a86aded26a211319649426d
This helps when testing to know on which tree/commit you based your
patches.
See "Providing base tree information" here:
https://docs.kernel.org/process/submitting-patches.html
I just tested your patchset on kernel 6.17.7, and my display no longer
works.
Also tested on torvalds/master tree commit 4427259cc7f7, with similar
results:
rzg2l-cpg 11010000.clock-controller: hsclk out of range
Hugo.
--
Hugo Villeneuve
