On 07/11/2025 08:54, Krzysztof Kozlowski wrote: > On Thu, Nov 06, 2025 at 07:42:23PM +0530, Swamil Jain wrote: >> From: Louis Chauvet <[email protected]> >> >> The dt-bindings for the display, specifically ti,am65x-dss, need to >> include a clock property for data edge synchronization. The current > > clock properties are called "clocks". Please rephrase commit msg or use > proper clocks to indicate you access here a clock (if that's the case). > >> implementation does not correctly apply the data edge sampling property. > > Where is "data edge sampling property"? I do not see it in this binding. > >> >> To address this, synchronization of writes to two different registers is > > How this binding achieves that "synchronization"? What are you even > describing here? > >> required: one in the TIDSS IP (which is already described in the tidss >> node) and one is in the Memory Mapped Control Register Modules. >> >> As the Memory Mapped Control Register Modules is located in a different > > And now another therm - MMCR... > > This commit msg is barely parseable - language is correct but it is a > mix of completely wrong terms. > > In case you used LLM to write this - don't. Ever. > >> IP, we need to use a phandle to write values in its registers. >> >> Fixes: ad2ac9dc9426 ("drm/tidss: Add support for AM625 DSS") >> Fixes: 5cc5ea7b6d7b ("drm/tidss: Add support for AM62A7 DSS") > > You still did not describe the actual bug being fixed here. >
Actually, NAK, because you ignored entire previous feedback! Best regards, Krzysztof
