On Thu, Oct 23, 2025 at 03:53:50PM +0800, yuanjie yang wrote: > From: Yuanjie Yang <[email protected]> > > Add DSI PHY support for the Kaanapali platform. > > Signed-off-by: Yongxing Mou <[email protected]> > Signed-off-by: Yuanjie Yang <[email protected]> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++ > 3 files changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index 4ea681130dba..7937266de1d2 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -577,6 +577,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { > .data = &dsi_phy_4nm_8650_cfgs }, > { .compatible = "qcom,sm8750-dsi-phy-3nm", > .data = &dsi_phy_3nm_8750_cfgs }, > + { .compatible = "qcom,kaanapali-dsi-phy-3nm", > + .data = &dsi_phy_3nm_kaanapali_cfgs }, > #endif > {} > }; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index e391505fdaf0..8df37ea50f92 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -64,6 +64,7 @@ extern const struct msm_dsi_phy_cfg > dsi_phy_5nm_sar2130p_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs; > > struct msm_dsi_dphy_timing { > u32 clk_zero; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 32f06edd21a9..93e53fb8b4fa 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -1518,3 +1518,26 @@ const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = { > .num_dsi_phy = 2, > .quirks = DSI_PHY_7NM_QUIRK_V7_0, > }; > + > +const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs = { > + .has_phy_lane = true, > + .regulator_data = dsi_phy_7nm_98000uA_regulators, > + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), > + .ops = { > + .enable = dsi_7nm_phy_enable, > + .disable = dsi_7nm_phy_disable, > + .pll_init = dsi_pll_7nm_init, > + .save_pll_state = dsi_7nm_pll_save_state, > + .restore_pll_state = dsi_7nm_pll_restore_state, > + .set_continuous_clock = dsi_7nm_set_continuous_clock, > + }, > + .min_pll_rate = 600000000UL, > +#ifdef CONFIG_64BIT > + .max_pll_rate = 5000000000UL, > +#else > + .max_pll_rate = ULONG_MAX, > +#endif > + .io_start = { 0x9ac1000, 0xae97000 },
These two addresses are very strange. Would you care to explain? Other than that there is no difference from SM8750 entry. > + .num_dsi_phy = 2, > + .quirks = DSI_PHY_7NM_QUIRK_V7_0, > +}; > -- > 2.34.1 > -- With best wishes Dmitry
