On 10/15/25 12:55 PM, Matt Coster wrote:
Hello Matt,
I see this pattern used throughout
the Renesas dts, but I'm just thinking how this will interact with the
powervr driver. The reset line is optional since some hardware
integrations manage it for us during the power-up/down sequences, which
appears to be the case here with the MSTP control (from my brief dig
through the Renesas TRM).
As far as I can tell, the pvr_power.c toggles the IP reset after the
IP clock were already enabled, so the IP should be correctly reset.
What kind of problem do you expect ?
I think I'm just being paranoid about the weirdness (to me at least) of
having one device be treated as both clock and reset line. Assuming this
is tested as working, I'm okay with it, especially as it seems to be the
norm for Renesas.
The combined clock/reset IP is not limited to renesas SoCs, there are
other SoCs which do the same thing (Allwinner "ccu", Marvell PXA
"soc_clocks" , nVidia Tegra "car", Qualcomm "gcc", Rockchip "cru", to
name a few). Usually the registers which control clock and resets are
shared in the same IP, but they control different (possibly related)
signals in the SoC.
Related, see my comments on the bindings patch (P1/3) about how clocks
are wired up in this SoC.
I tried to reply to that one, hopefully it makes some sense.
Looks like we've figured it out there, thanks for your comments!
Likewise, thank you for sharing the clocking details.
--
Best regards,
Marek Vasut
