On 10/14/25 1:52 PM, Matt Coster wrote:
Hello Matt,
diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
index c87d7bece0ecd..c9680a2560114 100644
--- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
@@ -13,6 +13,12 @@ maintainers:
properties:
compatible:
oneOf:
+ - items:
+ - enum:
+ - renesas,r8a77960-gpu
+ - renesas,r8a77961-gpu
I think this can just be renesas,r8a7796-gpu; most of the devices in the
dts for these SoCs appear to use the same pattern and the GPU is the
same in both.
Not really, the 77960 and 77961 are different SoCs, that is why they
each have different specific compatible. Of course, most drivers match
on fallback compatible, since the IPs are mostly identical, see this:
$ git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77961.dtsi
arch/arm64/boot/dts/renesas/r8a77961.dtsi: compatible =
"renesas,r8a77961";
arch/arm64/boot/dts/renesas/r8a77961.dtsi:
compatible = "renesas,r8a77961-wdt",
arch/arm64/boot/dts/renesas/r8a77961.dtsi:
compatible = "renesas,gpio-r8a77961",
...
$ git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77960.dtsi
arch/arm64/boot/dts/renesas/r8a77960.dtsi: compatible =
"renesas,r8a7796";
arch/arm64/boot/dts/renesas/r8a77960.dtsi:
compatible = "renesas,r8a7796-wdt",
arch/arm64/boot/dts/renesas/r8a77960.dtsi:
compatible = "renesas,gpio-r8a7796",
arch/arm64/boot/dts/renesas/r8a77960.dtsi:
compatible = "renesas,gpio-r8a7796",
I can turn the first entry into renesas,r8a7796-gpu to be consistent
with the legacy 7796 name for 77960.
Geert ?
+ - const: img,img-gx6250
+ - const: img,img-rogue
- items:
- enum:
- ti,am62-gpu
You also need to add img,img-gx6250 to the appropriate conditional
blocks below here for the number of power domains (in this case, 2) and
clocks (that's more complicated).
These older GPUs always require three clocks (core, mem and sys), but
it's not immediately clear from the Renesas TRM how these are hooked up.
I can see three "clocks" connected (fig 23.2 in my copy, clock details
from fig 8.1b):
Which revision of the RM is that ? There should be some Rev.M.NP at the
bottom of each page.
- Clock ZGφ: Appears to be a core clock for the GPU (3DGE). That would
make it our "core" clock.
This should be 600-700 MHz clock on M3-W , so that sounds like a GPU
core clock.
- Clock S2D1φ: Appears to be a core clock used on the AXI bus, making
it our "sys" clock.
This should be 400 MHz AXI clock, but wouldn't that make it "mem" clock
? I think this might be the clock which drives the AXI bus, used by the
GPU to access data in DRAM ?
- MSTP ST112: Appears to be a whole module on/off control of some
description, and definitely doesn't align with the missing "mem"
clock.
Maybe this is the "sys" clock, since it toggles the register interface
clock on/off ?
Do you have any further insights as to how Renesas have wired things up?
Please see above, maybe that helps a bit ?
--
Best regards,
Marek Vasut
