On 13/10/2025 20:01, Marek Vasut wrote: > Document Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58 > present in Renesas R-Car R8A77960 M3-W and R8A77961 M3-W+ SoC. > > Signed-off-by: Marek Vasut <[email protected]> > --- > Cc: Adam Ford <[email protected]> > Cc: Conor Dooley <[email protected]> > Cc: David Airlie <[email protected]> > Cc: Frank Binns <[email protected]> > Cc: Geert Uytterhoeven <[email protected]> > Cc: Krzysztof Kozlowski <[email protected]> > Cc: Kuninori Morimoto <[email protected]> > Cc: Maarten Lankhorst <[email protected]> > Cc: Magnus Damm <[email protected]> > Cc: Matt Coster <[email protected]> > Cc: Maxime Ripard <[email protected]> > Cc: Rob Herring <[email protected]> > Cc: Simona Vetter <[email protected]> > Cc: Thomas Zimmermann <[email protected]> > Cc: [email protected] > Cc: [email protected] > Cc: [email protected] > --- > See https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/13 > for related userspace bits. > --- > .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > index c87d7bece0ecd..c9680a2560114 100644 > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > @@ -13,6 +13,12 @@ maintainers: > properties: > compatible: > oneOf: > + - items: > + - enum: > + - renesas,r8a77960-gpu > + - renesas,r8a77961-gpu
I think this can just be renesas,r8a7796-gpu; most of the devices in the dts for these SoCs appear to use the same pattern and the GPU is the same in both. > + - const: img,img-gx6250 > + - const: img,img-rogue > - items: > - enum: > - ti,am62-gpu You also need to add img,img-gx6250 to the appropriate conditional blocks below here for the number of power domains (in this case, 2) and clocks (that's more complicated). These older GPUs always require three clocks (core, mem and sys), but it's not immediately clear from the Renesas TRM how these are hooked up. I can see three "clocks" connected (fig 23.2 in my copy, clock details from fig 8.1b): - Clock ZGφ: Appears to be a core clock for the GPU (3DGE). That would make it our "core" clock. - Clock S2D1φ: Appears to be a core clock used on the AXI bus, making it our "sys" clock. - MSTP ST112: Appears to be a whole module on/off control of some description, and definitely doesn't align with the missing "mem" clock. Do you have any further insights as to how Renesas have wired things up? Cheers, Matt -- Matt Coster E: [email protected]
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