On Wed, Jul 21, 2021 at 12:28 PM Sebastian Huber <sebastian.hu...@embedded-brains.de> wrote: > > On 21/07/2021 20:25, Gedare Bloom wrote: > >>>>> As far as I'm aware, SGIs can be enabled or disabled using > >>>>> GICD_ISENABLER0 > >>>>> just like > >>>>> > >>>>> PPI or SPI interrupts for both GICv2 and GICv3. Section 3.1.2 of the > >>>>> GICv2 > >>>>> architecture > >>>>> > >>>>> spec (IHI0048B) references this, though I have seen implementations > >>>>> where > >>>>> certain SGI > >>>>> > >>>>> and PPI interrupts are hard-wired enabled or disabled and that state > >>>>> can't be > >>>>> changed > >>>>> > >>>>> (which is also covered in this section). > >>>> Ok, on Qemu and the i.MX7D the SGI are always enabled. I would keep the > >>>> attributes like this until we have a system which is different. > >> Should a comment be added that says this? > >> > > Yes, in case someone else comes along to add support for a system that > > is different, it will help to give them some pointers. > > I addressed this with new attributes in the v2 patch versions: > > https://lists.rtems.org/pipermail/devel/2021-July/068276.html >
Aha. Thanks. We currently prefer a full patch set post after review, but this is fine with me. I would like to see the comment made in the gic sources themselves where the attributes get initialized specifically for this case of the SGI on these devices. > > -- > embedded brains GmbH > Herr Sebastian HUBER > Dornierstr. 4 > 82178 Puchheim > Germany > email: sebastian.hu...@embedded-brains.de > phone: +49-89-18 94 741 - 16 > fax: +49-89-18 94 741 - 08 > > Registergericht: Amtsgericht München > Registernummer: HRB 157899 > Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler > Unsere Datenschutzerklärung finden Sie hier: > https://embedded-brains.de/datenschutzerklaerung/ _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
