So after a little more diving into this, I have found why --strict-align is required. If the MMU is disabled, all memory is treated as device memory which requires strictly aligned accesses.
Kinsey -----Original Message----- From: devel <devel-boun...@rtems.org> On Behalf Of Kinsey Moore Sent: Friday, March 5, 2021 07:12 To: Sebastian Huber <sebastian.hu...@embedded-brains.de>; devel@rtems.org Subject: RE: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP Hi Sebastian, For AArch64, that would be SCTLR_EL1.A (bit 1). Even with that alignment checking disabled, I still see data aborts on misaligned accesses. The MMU is disabled during operation, so that wouldn't be the issue, either. From reading the spec on that bit, it would seem that AArch64 is accepting of misaligned writes by default, but that's not the behavior I've seen with the two ZynqMP boards I have on hand. There is also SCTLR_EL1.nAA which toggles allowance of accesses spanning 16-byte boundaries, but the feature controlling whether that bit functions is only mandatory from ARMv8.4 onward and is optional from ARMv8.2. Even so, the nAA bit only affects a small subset of load and store instructions. The section on unaligned accesses in the manual only references these two bits and the LSE2 feature that controls whether the nAA bit is functional. Kinsey -----Original Message----- From: Sebastian Huber <sebastian.hu...@embedded-brains.de> Sent: Thursday, March 4, 2021 23:54 To: Kinsey Moore <kinsey.mo...@oarcorp.com>; devel@rtems.org Subject: Re: [PATCH v1 7/7] spec/aarch64: Force strict alignment for ZynqMP On 04/03/2021 23:15, Kinsey Moore wrote: > Real hardware running AArch64 does not appreciate accesses misaligned > relative to the data size. This prevents generation of misaligned writes > which would throw exceptions. The patch set is fine independent of the following comment. To me this problem with misaligned access looks like an MMU/system configuration issue. For example in AArch32, you have to enable misaligned access in SCTL[A]. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
