On 12/11/18 3:33 PM, Joel Sherrill wrote: > The order in which threads are assigned to cores has changed since the > first smp work. It used to be from 0 up, now from the highest core > associated with a scheduler down. If that's the only difference, the > screen is out of date.
Good to know, this is what I am seeing. > > Even if the screen is a guide of what to expect in some cases. > > How does the smp support in sis switch back and forth between the > cores? Per cycle, instruction, etc. Qemu switches per instruction > translation block as I recall. The scheduling slice is (dynamically) configurable in number of clock cycles. I currently have it set to 50 but the smp tests works also at 1000. The scheduling overhead is ~ 10% at 50 cycles, so the slowdown is acceptable even for non-smp loads. My plan is to simulate each cpu instance in a separate host thread, and synchronize them on events in the event queue. Not quite sure how well that will work though ... :-)
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