The order in which threads are assigned to cores has changed since the first smp work. It used to be from 0 up, now from the highest core associated with a scheduler down. If that's the only difference, the screen is out of date.
Even if the screen is a guide of what to expect in some cases. How does the smp support in sis switch back and forth between the cores? Per cycle, instruction, etc. Qemu switches per instruction translation block as I recall. --joel On Tue, Dec 11, 2018, 9:24 AM Sebastian Huber < sebastian.hu...@embedded-brains.de wrote: > Hello Jiri, > > On 11/12/2018 15:15, Jiri Gaisler wrote: > > What is the status of the smptests of RTEMS 5 ? > > > > I have added SMP capability to the sis simulator, and have tested it > > with the smptests from rtems git. I have noticed that the reference > > output (*.scn) are not equivalent to what the simulator or real hardware > > outputs. It seems that the cpus are numbered backwards compared to the > > .scn files. > > the .scn files are not up to date. Also the test output is quite test > dependent and repeated test runs my produce different output. > > The best method to check if a test passed is to check if the > > *** END OF TEST XYZ *** > > > message is printed. Which real target did you use to run the tests? I > will do a test run tomorrow on a N2X. > > -- > Sebastian Huber, embedded brains GmbH > > Address : Dornierstr. 4, D-82178 Puchheim, Germany > Phone : +49 89 189 47 41-16 > Fax : +49 89 189 47 41-09 > E-Mail : sebastian.hu...@embedded-brains.de > PGP : Public key available on request. > > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. > > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel
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