There are architectures (for example some/many ARM Cortex-A) which have
different cache line sizes for data and instruction caches.
CPU kit and even BSP can be build for group of CPUs which differs
in cache line sizes as well and there are situations when maximum
alignment is not reported by rtems_cache_get_data_line_size.
Ensure, that allocated memory is aligned at least to CPU_CACHE_LINE_BYTES
which is in pair with compile time data structures allocation.
Signed-off-by: Pavel Pisa <p...@cmp.felk.cvut.cz>
---
cpukit/libcsupport/src/cachealignedalloc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/cpukit/libcsupport/src/cachealignedalloc.c
b/cpukit/libcsupport/src/cachealignedalloc.c
index a704859..bb93937 100644
--- a/cpukit/libcsupport/src/cachealignedalloc.c
+++ b/cpukit/libcsupport/src/cachealignedalloc.c
@@ -18,6 +18,9 @@ void *rtems_cache_aligned_malloc( size_t nbytes )
size_t line_size = rtems_cache_get_data_line_size();
if ( line_size > 0 ) {
+ if ( line_size < CPU_CACHE_LINE_BYTES )
+ line_size = CPU_CACHE_LINE_BYTES;
+
/* Assume that the cache line size is a power of two */
size_t m = line_size - 1;
--
2.1.4
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